Technical Insight
Silicon boosts InP MOSFET characteristics
InP MOSFETs with a HfO2 gate dielectric can deliver higher drive current, higher transconductance and a lower gate leakage if they contain a silicon passivation layer, according to researchers at the University of Texas at Austin.
This team claims that the improvements stem from addressing the poor quality of the interface between the gate and InP that tends to suffer from Fermi level pinning. Poor quality interfaces continue to plague the development of all forms of III-V MOSFET, which have the potential to offer a superior performance to silicon equivalents that are used in microprocessors, thanks to higher electron mobilities.
Engineers at Austin produced InP MOSFETs with a 1 nm thick silicon passivation layer and a 5.1 nm thick HfO2 gate, and compared their performance with control devices that just employed a 7 nm thick HfO2 gate.
The silicon interlayer tripled transconductance to 2.3 mS/mm, increased the drain current from 5.9 to 25.9 mA/mm and cut gate leakage from 3.9 × 10–2 to 1.32 × 10–2 A cm–3. Sub-threshold swing, which determines the voltage swing needed to switch the MOSFET from its off-state to its on-state, was reduced from 137 to 103 mV/decade.
Author Yen-Ting Chen says that the team now plans to investigate the role of the silicon interface passivation layer on III-V MOSFETs that feature other high-k dielectrics.
Engineers at Austin produced InP MOSFETs with a 1 nm thick silicon passivation layer and a 5.1 nm thick HfO2 gate, and compared their performance with control devices that just employed a 7 nm thick HfO2 gate.
The silicon interlayer tripled transconductance to 2.3 mS/mm, increased the drain current from 5.9 to 25.9 mA/mm and cut gate leakage from 3.9 × 10–2 to 1.32 × 10–2 A cm–3. Sub-threshold swing, which determines the voltage swing needed to switch the MOSFET from its off-state to its on-state, was reduced from 137 to 103 mV/decade.
Author Yen-Ting Chen says that the team now plans to investigate the role of the silicon interface passivation layer on III-V MOSFETs that feature other high-k dielectrics.
