News Article
EPC introduces Demo Board Using Enhancement Mode GaN Transistors
EPC9002 contains two GaN transistors and all critical components needed for optimal switching performance
EPC, the first company to produce Gallium-Nitride-on-Silicon transistors as power MOSFET replacements in all forms of computer, cell phones and flat-panel displays has unveiled the EPC9002. This development board will allegedly make it easier for developers to design with EPC1001 100V GaN Power Transistors.
With a 50 V maximum input voltage, 7 A maximum output current, the EPC9002 board has been designed to simplify the evaluation process of the EPC1001 GaN power transistor. It includes all the critical components needed for easy connection into any existing converter.
The 2” x 1.5” board is priced at $95 and along with two EPC1001 GaN transistors in a half bridge configuration, it has gate drivers, an on board gate drive supply and various probe points to facilitate simple waveform measurement and efficiency calculation.
Originally, GaN-on-silicon transistors were depletion-mode types in that they required a negative voltage to turn them off. However, the ideal mode for board designers would be to use transistors like today’s silicon-only MOSFETs which are usually non-conducting and require a positive voltage to turn them on.
A breakthrough made by EPC using standard MOS processing equipment has now enabled device-grade GaN to be grown on a silicon substrate to produce enhancement-mode FETs which have a similar fundamental operating mechanism to silicon-only MOSFETs.
GaN-on-silicon transistors, which have a comparable cost to their silicon-only counterparts, however, offer superior performance compared with silicon and SiC. They have lower resistance and the low temperature coefficient and exceptionally high electron mobility enable GaN devices to handle very high switching speeds.
The system also offers self-isolation enabling efficient monolithic power ICs to be fabricated economically and the transistor blocking-voltage may be customized as the distance between the drain and gate in a GaN transistor is proportional to the blocking-voltage.
