Scaling silicon ICs involves packing transistors closer and closer together, and this is pushing the power density on the chip towards its limit. Switching to III-V CMOS offers a promising way forward, but can this alternative technology be scaled to a few nanometers, manufactured in really high-volume and made in such a way that it has the look and feel of the silicon incumbent? Jesús del Alamo from MIT discusses the issues.

In 1971 the silicon industry entered a new era: production of the first programmable computer processors. The debut chip, the Intel 4004, purred away at 740 kHz and employed 2300 transistors with a line width of 10 μm.

Since then Intel has continually improved performance levels through scaling and technology innovation: its Core i3, Core i5, and dual-core mobile Core i7 processors that were released in the last year or so zip along at gigahertz speeds, and contain billions of transistors with feature sizes of tens of nanometers.

This tremendous improvement in chip performance that has occurred over the last four decades is a largely a result of scaling down the dimensions of the silicon transistor. Continuing in this vein will bring about further progress, but it is getting much harder with every new CMOS generation. That’s because with increases in transistor density, power dissipation has reached a practical limit and chips are running very hot. There is now no headroom left unless one is willing to use expensive new packaging and active cooling.

The way forward in this new “power constrained scaling” phase of the silicon industry is to reduce the transistor’s operating voltage. With silicon transistors, driving the voltage down while simultaneously enhancing transistor performance has become increasingly difficult, and the operating voltage for CMOS has bottomed at about 1 V for the last few generations of technology. This trend is a serious threat to further progress for the silicon IC. One way to alleviate this looming bottleneck is to switch to a channel with a far higher carrier velocity, which would allow further voltage scaling and better performance.

Several materials could fulfill this role, but by far the most promising are III-V semiconductors: their capabilities at high frequencies are proven; their reliability is also well established; and their deployment in the power amplifiers of mobile phones shows they could be used to manufacture chips in high-volumes in a cost-effective manner. In fact, III-Vs seem the obvious choice, because they are the only materials other than silicon with a wellestablished manufacturing and reliability record.

Room on the roadmap?

The bad news for the III-Vs is that there is a huge barrier for insertion of any new channel material into the CMOS roadmap. At the earliest insertion point that seems plausible today, the gate length will be at most in the 10- 15 nm range. This means that the entire transistor will fit in a footprint of less than 100 nm, making it small enough to integrate tens of billions of devices on a single chip. If a disruptive technology such as III-Vs is to stand any chance of success, it will also need to substantially outperform the best scaled silicon option of that day – a performance gain of 30-50 percent seems to be the minimum.

On top of this, a III-V-based approach must also offer the promise of a few scaled generations beyond the insertion node, plus cost-effective manufacturing and unprecedented levels of reliability. Do III-Vs have any chance of success?

One way to answer this question begins by seeing what we can learn from today’s devices. An excellent model system is the HEMT, a device with near terahertz capabilities that we have been investigating at MIT for the last few years. Our effort has focused on studying the logic characteristics of InGaAs and InAs HEMTs with gate lengths down to 30 nm. The encouraging news is that these devices exhibit logic characteristics, in terms of current drive and short-channel effects, rivaling state-of-the-art silicon MOSFETs with equivalent gate lengths.

Our transistor portfolio features HEMTs with a channel just 10 nm thick that includes a pure, 5 nm-thick InAs core (see figures 1 and 2). The InAlAs barrier in this structure has an effective thickness of just 4 nm, and the combination of this thin barrier and channel creates a device with excellent short-channel effects that can be scaled to 30 nm gate lengths.Devices with this gate length have excellent output characteristics with very good current drive. HEMTs operating in enhancement mode (VT=80 mV), an essential requirement for logic applications, have a peak transconductance 1.8 mS/μm at a VDS of just 0.5 V. Measuring performance at this source-drain voltage makes a lot of sense, because if III-V CMOS technology is to succeed, it will have to work at voltages substantially below 1 V.

 



Figure 1. Jesús del Alamo’s group at MIT have fabricated HEMTs on an InP substrate that feature a 10 nm-thick channel, which includes a 5 nm-thick, pure InAs core surrounded by an InGaAs cladding. T he barrier is InAlAs, lattice matched to InP. There is a low resistance InGaAs/InAlAs cap above a thin InP etch-stop layer. The gate is fabricated through a triple-recess process, and its stack includes platinum in its bottom layer, which is driven into the barrier in a thermal step. This leads to an effective reductionin the InAlAs barrier thickness to about 4 nm

 



Figure 2. Transmission electron microscopy reveals a gate length for the HEMT of 30 nm

 

For logic applications, subthreshold characteristics are more relevant (see Figure 3). Our measurements on 30 nm gate length devices show the drain current dropping sharply below threshold, and the subthreshold swing, which characterizes this drop off, is 73 mV/dec. In addition, the threshold voltage depends little on the value of VDS. This is an important figure of merit in logic applications, called DIBL for drain induced current lowering, because it insures the reliable operation of the transistors in diverse circuit environments. Our device has a DIBL of 85 mV/V. This value and that for the subthreshold swing are as good as the best silicon MOSFETs of similar gate lengths.

 



Figure 3. The drain current of InGaAs HEMTs drops off rapidly below threshold.

 

Though less relevant for logic applications, these devices also display remarkable high-frequency characteristics. At a VDS of 0.5 V, they have a current gain cut-off frequency ft of 601 GHz and a power-gain cut-off frequency fmax of 609 GHz. As far as we know, this is the first transistor of any kind, on any material system, that simultaneously exhibits both ft and fmax in excess of 600 GHz. The important implication of these results is that minimizing parasitics and enhancing short-channel effects not only optimizes logic operation - it also yields extraordinary frequency response. This bodes well for the prospects of a future ultra-low power, mixed-signal, terahertz-logic technology based on III-Vs.

One way to make a meaningful assessment of the logic potential of candidate device technologies is to define a figure of merit that integrates performance and shortchannel effects. Since key goals in scaling are to maximize the “on” current and minimize the “off” current, a suitable figure of merit is the value of ION for a fixed IOFF at a fixed operating voltage.

We have determined this figure of merit for our HEMTs, and found that it not only exceeds that for current CMOS technology – it beats that predicted for future generations of the incumbent technology too (see Figure 4). This performance gap is more impressive than it first appears, because silicon MOSFETs have a typical source resistance of 80 Ohm.μm, nearly three times lower than that of our InAs HEMTs. Clearly, there is plenty of headroom for improvements in the performance of our III-V transistors, so long as the extrinsic portion of the device can be properly engineered. One wonders, in fact, how far III-Vs could go?

 



Figure 4. “On” current for an “off” current of 100 nA/μm at VDD=0.5 V as a function of gate length for InAs HEMTs made at MIT. This is a figure of merit that aggregates performance and short-channel effects. For reference, recent scaled silicon CMOS technologies are shown. These data are courtesy of D. Antoniadis (MIT) and are based on detailed analysis of Intel’s High Performance CMOS technologies presented at IEDM. Also added are projections from the International Technology Roadmap for Semiconductors

 

It takes some work to answer this question. The first step is to extract the electron injection velocity at the virtual source, which is the velocity that matters to determine the current in a FET in saturation. We have recently measured this in great detail for different channel compositions, and obtained values in excess of 3x107 cm/s for 30 40 nm gate-length devices operating at VDS=0.5 V (see Figure 5). This set of results shows that increasing the indiumcontent in the channel increases injection velocity, and that is it possible to reach values that are twice those seen in strained silicon. What’s more, this doubling of speed is possible with operating voltages that are less than half of those used in strained silicon CMOS. Any evaluation of the true potential of III-Vs must also consider potential implications of their low effective mass, such as their small density of states (DOS) and corresponding low quantum capacitance. This could blunt the scaling of the vertical dimensions of the FET and its overall scalability.

 



Figure 5. Injection velocity at the virtual source in InGaAs and InAs HEMTs fabricated at MIT as a function of gate length at VDD=0.5 V. For reference, results from bulk and strained silicon CMOS are also included (VDD=1.1-1.3 V). In spite of operating at less than half the voltage, InAs and InGaAs HEMTs significantly outperform silicon MOSFETs

 

To address these concerns we have recently carried out a theoretical and experimental study of gate capacitance in advanced InGaAs and InAs HEMTs. Our conclusion: there is a significant increase in the DOS effective mass and the sheet charge density in the InAs channel resulting from the non-parabolicity of its conduction band coupled with channel quantization and biaxial compressive strain. Based on these findings, we believe that it is eminently feasible to produce III-V transistors with 10 nm gate lengths operating at VDD=0.5 V, which have a sheet carrier density in the mid 1012 cm-2 range. The upshot of these two recent results – the injection velocity and scaled gate capacitance – indicates that a 10 nm gate-length III-V FET with a thin InAs channel should be capable of reaching a drive current of about 1.5 mA/μm (this will require a source resistance of 80 Ohm.μm). If our predictions are correct, III-V CMOS can deliver a level of performance well above that of the silicon equivalent, even assuming the most optimistic scenario for the incumbent technology.

But is it possible to turn hope into reality by reengineering our HEMTs, so that they can scale down to these dimensions and realize the desired level of performance? Probably not. Substantial gate leakage current is already present at 30 nm gate lengths (see Figure 3). This is because of the thin InAlAs barrier that separates the gate from the channel. Any further reductions in gate length will demand additional gate barrier thickness scaling yielding intolerable gate leakage currents. So, our HEMTs are already very close to their scaling limit, at least from the logic point of view. The inevitable conclusion is that a future 10 nm III-V logic FET will require a high dielectric constant (“high K”) gate dielectric, something that will only be possible via profound re-engineering of the device.

The development of a reliable, manufacturable gate stack that includes a high-K gate dielectric and yields a highquality semiconductor interface with a III-V compound semiconductor is as intriguing as any problem in modern semiconductor technology. Like all great challenges, it has been attracting great interest. Recent research from around the world has shown the great promise of ex-situ Atomic Layer Deposition (ALD) and MOCVD for depositing high-K dielectrics on suitably treated InGaAs surfaces. ALD, in particular, has demonstrated its capability to engineer the bonding structure at the III-V surface. This holds the key for Fermi level unpinning and attaining a low density of interface states.

The gate stack is actually one of a handful of very challenging technical problems that must be solved before a III-V CMOS technology can become a reality (Figure 6). Scaling down transistor size is another major concern. Will it be possible to scale III V transistors to the required dimensions, while preventing excessive short-channel effects and realizing the low levels of parasitic resistance that are required? We can’t tell at this point. Straight scaling of the extrinsic region of a modern HEMT to the dimensions required for a 10 nm III-V MOSFET would result in an external resistance two orders of magnitude too high. Addressing this is going to require extensive technology development and simulations. Fortunately, our HEMTs have also served to calibrate modern device simulators, which reproduce their characteristics quite well. These are valuable tools to predict device characteristics in the 10 nm range. If planar devices fail to yield the required short-channel effects at the desired lengths scales, we can resort to developing threedimensional devices. In the silicon domain, FinFETs and nanowire transistors are serious contenders for the 22 nm CMOS node and perhaps beyond. Three-dimensional device demonstrations in III-Vs give hope to this avenue. GaAs FinFETs and InAs nanowire transistors with impressive characteristics have been demonstrated at Purdue, Lund University and other places.

 



Figure 6. This diagram outlines key challenges to a manufacturable III-V CMOS logic technology

 

Dealing with the holes

Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon. Mobilities in silicon have improved through the addition of strain in the material, with the performance of the pchannel now approaching that of its n-type cousin. It will be interesting to see if the same trick will work for the arsenides.

Other options for the p-channel are also available. Measurements have revealed antimonides mobilities in the 1500 cm2/V.s range and p-channel transistors have already been fabricated. Germanium transistors are also of interest. Germanium has a high hole mobility that is enhanced through strain. It also has the advantage of being nearly lattice-matched to GaAs. This suggests a possible CMOS platform in which germanium and III-V transistors are integrated side by side.

Last but by no means least on the list of major challenges is the need for a future III-V CMOS technology to closely “look and feel” like the silicon incumbent. Meet this goal and III-V CMOS can then exploit the tremendous economy of scale in the silicon industry. The most likely incorporation of III-Vs in the CMOS road map is via an enhancement to the existing technology through the insertion of a III-V channel - much like the recent additions of high-K/metal gates or strain. Exactly how this plays out will be influenced by what emerges as the best option for the p-channel device, and it is possible that the future will witness two different channel materials sitting side by side, on top of a silicon wafer.

With III-Vs knocking on the door of the CMOS roadmap, it’s clear that the present generation of III-V scientists and engineers have an opportunity ahead of them to shape the future of mainstream electronics. Has there ever been a better time to be a III-V semiconductor technologist?


 



Acknowledgements

Research on III-V logic technology at MIT has been sponsored in the last few years by the FCRP Focus Center on Material, Structures and Devices (MSD) and Intel Corporation.

Further reading

S. Oktyabrsky and P. D. Ye (Editors), “Fundamentals of III-V Semiconductor MOSFETs”, Springer 2010.

M. Heyns and W. Tsai (Guest Editors), MRS Bulletin, Special Issue on “Ultimate Scaling of CMOS Logic Devices with Ge and III-V Materials”, Vol. 34, No. 7, July 2009.

M. Radosavljevic et al., “Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications.” 2009 IEEE International Electron Devices Meeting, p. 319.

D.-H. Kim, J. A. del Alamo, D. A. Antoniadis, and B. Brar, “Extraction of Virtual Source Injection Velocity in sub-100 nm III-V HFETs.” 2009 IEEE International Electron Devices Meeting, p. 861. D.-H. Kim and J. A. del Alamo, “30 nm E-mode InAs PHEMTs for THz and Future Logic Applications.” 2008 IEEE International Electron Devices Meeting, p. 719.