Uniting III-Vs And Germanium For CMOS
Unleashing the high electron and hole mobilities of InGaAs and germanium in an evolutionary CMOS architecture is possible by introducing a common gate stack. This can be formed by a combination of a sulfur-based treatment and deposition of aluminum oxide, and results suggest that this process does not hamper the performance of these novel devices, says IMEC’s Thomas Hoffmann.
It is nigh on impossible to overstate the progress of CMOS technology since its invention in the 1960s. Most of these tremendous gains have resulted from shrinking the size of the transistors, and for the first four decades no major modifications were needed to the design of the device that exploited the great interface between silicon and silicon dioxide.
But this pairing of silicon and its native oxide could only go so far, and more recently progress has hinged on the introduction of new materials. For example, in 2007 Intel introduced a high-k dielectric based on the far more exotic material, hafnium, into its production process to prevent high leakage currents in its 45 nm node Core 2 Duo process.
Advances like this, along with the introduction of metal gates, provide a massive boost to everyone developing alternative forms of CMOS, such as those who dream about replacing the conventional silicon channel with much higher mobility materials, like germanium and III-V compounds.
Although there is still much to do to make this dream a reality, some progress has been made. In particular, breakthroughs in germanium and InGaAs surface channel MOSFETs have brought the research community far closer to unleashing the potential of these high-mobility channel materials, for high drive current at scaled supply voltage.
Efforts, including those by our team of researchers at the European research center imec, have shown that germanium-based channels are very promising for making high-performance p-FETs. And similar developments, at Intel in particular, have unveiled the great potential of InGaAs channels for the n-FET.
Integrating those two strong contenders under a conventional CMOS process is formidable, and requires overcoming a handful of challenges: growth of selective and defect-free high-mobility materials on a silicon substrate, despite the intrinsic, large-lattice-mismatch; formation of ultra-low resistance contacts to a III/V material; and excellent electrical passivation of the interface between the high-k dielectric and the alternative channel materials.
The latter challenge is particularly tough in the case of CMOS integration, because a common gate stack strategy is necessary in order to passivate the different materials for forming surface-channel devices: germanium (p-FET) and InGaAs (n-FET). We are now working on this problem, and considering a range of architectures for combining a III-V n-MOSFET and a germanium p- MOSFET, such as that shown in Figure 1.
Figure 1: A common gate stack is essential for enabling the high mobilities of germanium and InGaAs to make an impact in future CMOS technology
Nearly all well-functioning high-k dielectrics that employ a low-equivalent-oxide thickness (EOT) material on silicon still start with a thin Si/SiO2 interfacial layer, and the highk dielectric is then deposited on top. This route is chosen because the pairing of silicon and its native oxide is a great combination in terms of material quality. A great deal of effort has been applied to mimicking this silicon/SiO2 interface on germanium and III/V materials by introducing an ultra-thin silicon cap that is just a few monolayers thick and can act as a surface passivation layer. Germanium channels have benefited from this approach, and we have shown that this can lead to improvements in pMOS devices. (This is not the only route to passivating germanium surfaces, and alternative approaches include thermal deposition of a GeO2 or GeON interfacial layer, and deposition of some high-k dielectrics).
Turning to the III-V devices operating in inversion mode (the configuration that’s suited to digital applications and employed in silicon), the key issue here is to address the near-midgap Fermi level pinning. This results from the high density of states at the high-k/III-V interface, which leads to a less efficient channel potential control from the gate. The implication is that the kind of high-k material used as a gate oxide probably has a secondary impact on the nature and energy distribution of the interface states and, hence, on the Fermi level pinning point. However, the density of interface traps (Dit) can be strongly affected by the type of surface preparation used, which could be cleaning or various passivation treatments.
To address the integration of these high-mobility MOSFETs, we have proposed a common gate stack approach for both the germanium p-MOSFET and InGaAs n-MOSFET. This is based on the duality of the oxidesemiconductor interface properties found on the germanium and In0.53Ga0.47As MOS samples. Both of these have undergone a sulfur-based wet-chemical treatment, followed by the growth of an Al2O3 common gate dielectric by atomic-layer deposition (ALD) (see figure 2).
Figure 2. imec has fabricated MOS capacitors with a common gate stack process
After native oxide removal, both of these substrates were treated in ammonium sulfide solution, prior to ALD of Al2O3 in a reactor chamber. This is followed by postdeposition anneals at 400 degress C with forming gas. The sulfur treatment process helps to reduce formation of a native oxide, according to our images of the aluminium oxide capped samples (figure 2).
To realize high performing devices, it is essential to not only have high channel mobility, but also good “on/off" switching characteristics. Turning the device from its “on" to “off" configuration causes a shift in the channel energy level from a position close to the band edge (conduction band for n-FET, and valence band for p-FET) towards the mid-gap. Efficient swing of the channel potential by the gate bias requires a low level of interface traps in the range of interest (nFET: upper half of the bandgap; pFET: lower half of the bandgap), so it is critical to obtain a sufficiently low level of these traps in those respective regions of device operation.
This is possible, according to our measurements of the density of interface traps in germanium and InGaAs MOS interfaces that have been fabricated using a process capable of producing a common gate stack (see Figure 3).
Figure 3: Distributions of the density of interface traps, which are deduced from measured conductance data, show the relatively low number of traps near the valence band of germanium and the conduction band of InGaAs
This data reveals high levels of interface traps in germanium on the conduction band side, and in InGaAs on the valence band side, which can be attributed to acceptor-like and donor-like traps, respectively. A low density of interface traps at the germanium valence band edge suggests less donor-like traps and implies that more free carriers (holes) can be collected in the p-channel. Similarly, the low density of interface traps levels near the InGaAs conduction band edge means less acceptor-like traps and more free electrons for forming the n-channel.
Such features are encouraging. Not only do they make transistor operation possible - they allow the high carrier mobility nature of the germanium p-MOSFET and InGaAs n-MOSFET to be unleashed.
To verify this promise, we have fabricated inversion-type surface-channel MOS transistors with 8 nm of Al2O3 on both germanium substrates with n-type doping of 3 x 1016 cm-3, and In0.53Ga0.47As substrates with ptype doping of 1 x 1017 cm-3. These have been produced with exactly the same oxide stack process that we have already described.
These self-aligned germanium and InGaAs MOSFETs that are built with common gate stack design have produced a very encouraging set of results. These include drain currents of 600 mA/mm and 200 mA/mm at a 2.5 V gate bias swing for InGaAs and germanium MOSFETs respectively. Both transistors have a gate length of 1.5 μm (see Figure 4).
Figure 4: imec’s InGaAs and germanium FETs show promising drain currents and mobilities that are comparable to the best results realized anywhere
The mobilities in the channels of our common gate stack MOSFETs with 10 μm gates are comparable to the bestreported values anywhere: Hole and electron field-effect mobility values are 400cm2/V-s and 1300cm2/V-s, respectively. Producing these results with the common gate stack is a very important breakthrough for the future of alternative CMOS architectures, because it shows that this approach has the potential to draw on the strengths of III-Vs and germanium.
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