IEDM to showcase record-breaking III-Vs
This year’s IEEE Electron Devices Meeting (IEDM) will include coverage of a 400 GHz GaN HEMT, an InGaAs terahertz transistor, an InGaAs FinFET for low-power logic and the world’s first InGaAs MOSFET on an insulating substrate.
At IEDM 2010, which will be held in San Francisco from 6-8 December, a team from HRL will be claiming the speed record for a GaN HEMT.
The GaN-on-SiC transistor produced by this US defence giant has a 40 nm gate and produces a cut-off frequency of 220 GHz and a maximum oscillation frequency of 440 GHz.
According to HRL, one of the challenges associated with making a transistor out of GaN is the realization of a good electrical contact with the material, given its high resistance. The team overcame this by re-growing the ohmic contacts using molecular-beam epitaxy.
Ultra-high speed transistors will also be reported by a team led by Teledyne Scientific. This effort has led to a 1-THz InGaAs Transistor with “good” gain.
This team’s transistor is a 50nm gate-length enhancement-mode PHEMT that was built on InP has good transconductance (1.7S/mm) at moderate voltage levels.
Key to its performance are the short gate length and a small channel (10nm thick), which maximize carrier transport and minimize contact resistance and capacitance parasitics. The 1.7S/mm transconductance at 1THz (fmax) was achieved at 0.75V input voltage.
The meeting will also detail the efforts of a team led by University of Tokyo that has fabricated the world’s first InGaAs MOSFET built on an insulating substrate, and also the thinnest InGaAs MOSFET ever made, with a tiny 3.5nm channel.
Nonconducting substrates are key to the eventual integration of such devices with silicon CMOS architectures because they reduce short-channel effects. This device has dual gates and demonstrated good on/off characteristics (~107) and transconductance.
The team direct wafer-bonded their transistor to silicon. They avoided creating unwanted source-drain junctions, which, because of the extremely thin films that make up the device, would have been difficult to anneal and would have made ion implantation difficult. Instead, they substituted an n-doped accumulation-mode channel.
Meanwhile, a partnership between Intel and IQE will report the development of a InGaAs FinFET for low-power logic.
FinFETs are nanoscale transistors with long, thin channels surrounded by multiple gates that provide superior on/off control versus planar devices. InGaAs, meanwhile, is a compound semiconductor that yields faster, more energy-efficient transistors than silicon.
FinFETs made from InGaAs may make possible ultra-dense yet low-power logic circuits. The first surface-channel InGaAs FinFET was described at the 2009 IEDM, but this year a team led by Intel will discuss InGaAs quantum-well FinFETs with enhanced overall electrical performance, including good control of troublesome short-channel effects. The performance was made possible by 35nm-wide and smaller fins; ultra-small 5nm gate-to-drain and gate-to-source separations; a high-k gate dielectric, and a simplified source/drain architecture.
List of papers:
(Paper #6.1, “Non-Planar, Multi-Gate InGaAs Quantum-Well Field Effect Transistors with High-k Gate Dielectric and Ultra-Scaled Gate-to-Drain and Gate-to-Source Separation for Low-Power Logic Applications,” M. Radosavljevic et al, Intel/IQE, Inc.)
(Paper #3.1, “Extremely-Thin-Body InGaAs-on-Insulator MOSFETs on Si Fabricated by Direct Wafer Bonding,” M. Yokoyama et al, University of Tokyo/NIAIST/Sumitomo Chemical Co.)
(Paper #30.6, “50-nm E-Mode InGaAs PHEMTs on 100-mm InP Substrate with fmax > 1-THz,” D.-H. Kim et al, Teledyne Scientific Co./M.I.T.)
(Paper #30.1, “220-GHZ ft and 440-GHz fmax in 40-nm GaN DH-HEMTs with Re-Grown Ohmic Contacts,” K. Shinohara et al, HRL Laboratories/Jet Propulsion Laboratory)