The 2.2 kW static induction transistor developed by Microsemi is destined for success. It delivers unprecedented powers and a long lifetime, and it allows UHF radar manufacturers to build systems with far fewer components, say the company’s Mike Mallinger, Bruce Odekirk, Mar Caballero and Francis Chai.

Designers of defense radar systems are always on the look out for transistors that take power output to a new level. If they adopt such devices into their radar systems, they can increase detection range and improve sensitivity.

At Microsemi, which is headquartered in Irvine, California, we have recently been piquing the interest of these radar system designers with our SiC static induction transistor (SIT) that raises the bar for pulsed output in the UHF band. This device, which we expect to support the next generation of defense radar systems, is in the final stages of qualification and will be in initial production before the year is out. Volume production is slated for early 2011.

The SiC SIT structure is a new technology. So to ensure that the product can be manufactured in high volumes, while always delivering a high-quality performance, we have made significant investment in several areas: wafer supplier qualification; high-power chip design; transistor packaging; transistor pre-matching network optimization; and RF performance characterization and reliability testing. The effort made in each of these areas is detailed below.

We have invested a great deal of time and effort in qualifying multiple wafer vendors. This will allow us to address the high quantity of product required to support volume production of our SiC RF and power switching products. Introducing material analysis procedures has provided confirmation of the quality and the consistency of the epiwafers from each of these suppliers. Routine incoming SiC epiwafer metrology includes cross-polarizer imaging (see Figure 1), AFM surface sampling scans (see Figure 2), and Nomarski microscopy imaging.



Figure 1. The lack of features in crosspolarized images of the epiwafers sourced by Microsemi indicates the high quality of the material



Figure 2. AFM images of Microsemi’s SiC epiwafers indicate their low level of surface roughness

All these assessments, which can be made on either 3–inch or 4 inch wafers, are recorded via digital data capture. This information can be recalled for reference and analysis. These digital files are frequently compared to both incoming localized laser scattering (LLS) defect maps provided by the epiwafer vendors and final die sort maps.

These types of comparison have proved extremely beneficial: they have enabled us to provide constructive feedback to the epiwafer suppliers; and they have also guided wafer fab process improvements. Thanks to all this effort we have established sources of material that are prepared to supply our volume production requirements for the next 10 years and beyond.

Within our 4-inch silicon power chip fab in Bend, Oregon, we have created a completely self-contained wafer manufacturing capability. The processes established at this facility include heated implants at up to 1000 °C and implant annealing at up to 1700 °C.

All the tools in this fab that are used for SiC device production are capable of processing both 3-inch and 4- inch SiC. Today all our manufacturing is carried out on the smaller of these sizes, but over the next two years we plan to migrate to the larger format. Our installed 3-inch wafer capacity is capable of supplying all projected radar programs over the next several years. Switching to 4-inch production will more than triple our capacity, and also increase tool redundancy.

Scaling-up

Our first prototype transistor cell produced only a fraction of the 2kW output power that’s possible with our latest product. But this device has been incredibly useful, providing an important building block for the fabrication of our 2.2 kW SIT. It has enabled us to establish our design rules, such as transistor channel width and length. These critical design rules have been subsequently validated by hooking up real devices with probes and extracting their electrical parameters. Devices that we have created adhere to these rules, indicating optimization of the fabrication processes and unit cell RF power performance.

To realize the high output powers demanded by applications such as pulsed radar, we have had to significantly up-scale the transistor cell size. Scaling is not trivial, because increasing chip power density does not necessarily result in amplifier output power scaling. That’s because thermal issues can hamper performance, which are related to the extremely high output powers produced by the chip.

However, by optimizing chip geometry we have been able to scale the device without any loss in performance. This has been realized by first performing experiments with design factors such as transistor cell size, chip geometry and chip thickness. Evaluating these results has enabled us to build devices that produce output powers approaching the theoretical transistor periphery-scaling factor.

All the customers that we are targeting with our 2kW transistors demand operational lifetimes in excess of 30 years. To meet this requirement we house our SIT in a hermetically sealed package, use gold-wiring throughout, and employ package plating and a gold-tin seal. History is on our side, because this approach has a proven reliability, having already served successfully in many highly demanding applications. However, due to the substantial increase in overall RF power and power dissipation, a new design is being implemented. This includes qualification of multiple suppliers. Our 2 kW device realizes such a high output power by combining several high-power transistor, multi-cell chips. To ensure the highest levels of repeatability and consistency in RF performance, highly precise automated die-attach and wire-bond machines are used in production.

Driving the SIT

The SIT is designed to operate at full power over 406- 450 MHz, a lower spread of frequencies within the UHF band. To do this it should be biased in “class AB, Common Gate” and run with a drain supply at 125 V. The terminal impedances are only a few Ohms, so an external matching network is needed to transform the impedance from the transistor up to 50 Ohms for device characterization and use. Fixture optimization includes a complete “load pull” analysis of the transistor, which can confirm that the matching network is designed for the best overall performance.

One of the benefits of load pull analysis is that it yields valuable information on device performance. It can quickly determine the optimum input and output device impedance over the band of interest, and rapidly deliver a trade-off analysis on critical RF performance parameters. We use these load pull impedance values as a target for the design of the input and output circuit-matching networks.

The typical input and output contours for a single frequency are shown in Figure 3. These contours offer an indication of how sensitive the device is to impedance changes. We obtain contours and optimum input/output impedance for each frequency across the band of interest. Our SiC SIT is a depletion mode device. Consequently, application of a gate bias is needed to turn the product ‘off’ before applying the drain bias. To aid the driving of the SIT, we include a ‘source pulser’ design with the RF test fixture to control the entire DC and RF functioning of the device. This new circuit technology will hopefully help to speed up our customer’s implementation of our products into their power amplifiers.

 



Figure 3. Source pull (left) and load pull (right) analysis offers a quick way to determine the optimum input and output device impedance over the band of interest

 

The primary function of the source pulser is to set an appropriate bias level for the device. The pulser’s main component is a high-speed analog switch that toggles between an off-voltage of +15 V and an on-voltage of 3- 5 V. The bias switching parameters are synchronized with the RF pulse.



A “source pulser” board is used with an RF test fixture to control the DC and RF behavior of the SiC SIT

 

When we start to manufacture our SIT in full production, we will add a bias sequence feature to ensure a proper power-up sequence during RF tests. Future efforts in this area may include the development of highly compact and efficient ASIC versions of the pulser assembly. Our SIT is designed to deliver incredibly high, pulsed powers. To verify that every product is capable of delivering this level of performance through its lifetime we will subject every transistor to a full functional set of tests prior to shipment. Due to the high voltages and currents associated with the driving of the device, the test procedure accommodates the latest operator safety procedures and power handling.

 



Microsemi’s SIT, which is shown with the lid off, is shipped in a hermetically sealed package. Gold wiring is used throughout

One of the strengths of our SIT is its ability to operate over a wide range of conditions, from very high peak powers at medium pulses to very long pulses at high duty factors. Thanks to its versatility of driving conditions, the SIT can support a wide range of applications. So to help potential customers evaluate what our SIT can do for them we have characterized this transistor for operation at conditions beyond those listed on the standard data sheet. To do this, we have made substantial investments in RF metrology and also developed highly automated test software. The reward of these efforts is the characterization of our products over multiple test conditions with very high levels of accuracy and repeatability. We believe that our SIT will have a massive impact on the design and build of the next generation of radar systems, and also their operational life, which is typically more than 35 years. We expect uptake of our SiC devices to be high. They can slash the number of components that a radar system needs, making it far smaller and cheaper. What’s more, the introduction of SiC into radar systems can cut maintenance costs and greatly expand operating life. Making a transition to a new product always involves some effort, because new devices behave differently and require new design rules. But we are convinced that this effort is justifiable, because our SIT offers great performance, alongside the consistency and reliability that designers of radar system are looking for.

 



Microsemi has a Centrotherm HV 100 high temperature implant anneal system in its power chip fab in Bend, Oregon. This tool is capable of operating at up to 1700oC