Technical Insight
Research Review: Navy unveils novel HBT
RESEARCHERS at the Naval Research Laboratory in Washington DC claim to have produced the first InAlAsSb/InGaSb DHBTs with an InAsSb emitter and sub collector.
Introduction of this ternary emitter has led to significant improvements in DC and RF performance. This transistor, which is based on materials with a 6.2 Angstrom lattice constant, has a collector current density of 1.9 x 105 A/cm2, a breakdown voltage in excess of 2.5 V, and values for the cut-off frequency and maximum oscillation frequency of 59 GHz and 34 GHz, respectively.
According to corresponding author James Champlain, these results show that this particular DHBT could serve many applications demanding low powers, high frequency performance, or both. Examples include deployment in A-to-D and D-to-A converters; ultra-linear low-noise amplifiers; and radar and imaging systems, especially those operating at terahertz frequencies.
One of the strengths of the team’s transistor is its low power consumption, which is a major plus point in battery-powered, portable applications.
“Reduction of battery weight and extended lifetime are critical in applications where weight and space are limited, such as space-based applications,” says Champlain. “Alternatively, in large distributed systems, such as some large phased array or imaging applications where power must be distributed to each cell of the system, reduced power consumption is critical in achieving practical applications.”
Solid-source MBE was used to form the DBHT epistructures that included a complex buffer (see figure for details). Standard processing and e-beam lithography techniques formed transistors from these epiwafers with a 2 x 10 μm2 emitter.
Characterization revealed base and collector ideality factors of 1.5 and 1.0, respectively. Series resistance was relatively low, thanks to the introduction of the InAsSb emitter and sub-collector layers.
Champlain says that the team will now work on improving DHBT performance through modifications to the device’s design layout and its material structure. This could involve reducing the area of the device, which should cut capacitance. Optimizing the selection of III-V layers offers another opportunity to increase transistor performance.
“Currently the device’s design includes a quaternary collector,” explains Champlain. “Classically, mixed alloys, such as ternaries and quaternaries, have poor thermal conductivity compared to binary alloys. Therefore, alternative collector designs and/or process technologies, such as substrate transfer, may be needed to capture the full benefit of these devices.”
J.G. Champlain et al. Elec. Lett. 1333 46 (2010)
