Sematech builds III-V transistors on large silicon wafers

Back in the twentieth century, the route to making faster, cheaper silicon chips was clear-cut: simply reduce the size of the transistor. But if such an approach had been adopted in recent years, it would have failed to deliver the gains in performance needed to keep pace with Moore’s Law. To maintain the level of progress prescribed by that Law, foundries have modified the standard silicon MOSFET and introducing new, more exotic materials. One of these is HfO2, which is used as the gate material. This replaces SiO2, a dielectric that would now lead to unacceptable increase in leakage current with transistor scaling. Another change is the introduction of silicon germanium, which is used to strain the pMOS device and speed the passage of holes from source to drain. The trend of incorporating a wider palette of materials is set to continue – the International Technology Roadmap for Semiconductors is advocating a move away from silicon transistors from 2015, when the 11 nm node will be rolled out. III-V MOSFETs are widely viewed as the most likely successors. However, despite their rich, long history of development, there is still a great deal to do before compound semiconductor transistors can be churned out in their millions at the world’s leading foundries. Development of III-V MOSFETs dates back to the 1960s. Then, just like now, the appeal of turning to this class of material stems from its very high electron mobility, which promises to lead to far faster chips. Finding a gate material that forms a high-quality interface with compound semiconductors has been one of the biggest obstacles to realizing such a device. SiO2 was quickly discarded in favor of other silicon compounds, sulfur passivation techniques, gates made from Ga2O3 and Gd2O3 oxides, and more recently, atomic layer deposition of aluminum oxides. There has also been a switch from a GaAs channel to an InGaAs one that sports superior transport properties. Nearly all of this work has involved a native substrate for III-V transistor development – reports of device fabrication on silicon substrates, the only material platform enabling a practical successor to silicon CMOS, have been few and far between. And almost all these efforts have used silicon substrates that are far too small to be processed by leading silicon foundries equipped with state of the art toolsets. The one exception is an effort by Sematech, a US-based nonprofit consortium of major semiconductor and chipmanufacturing equipment makers that performs basic research on chipmaking. At the recent International Electron Devices Meeting, Sematech front-end process device engineer Richard Hill detailed the fabrication processes and device results of In0.53Ga0.47As MOSFETs with varying gate lengths that were formed on 200 mm silicon wafers using state-of the-art manufacturing tools. “Our devices have been manufactured using a VLSI toolset, with processes that could be carried out in any one of the big foundries or IDMs,” says Hill. Turning to VLSI enables the fabrication of chips with very high levels of integration and a very small pitch, attributes that are impossible to realize using traditional III-V transistor manufacturing methods. Encouraging results MOSFETs produced by Sematech’s engineers have promising characteristics. The spread of the threshold voltage for these transistors is far tighter than it is for those produced using traditional III-V processing technologies, and similar to that of batches of silicon CMOS transistors (see Figure 1). The electron mobility in the III-V MOSFETs with a gate length of 20 μm peaks at 2000 cm2/Vs, a value roughly four times higher than that realized in equivalent silicon transistors.     Figure 1. The spread of threshold voltage in the III-V transistors made by Sematech is comparable to that of a batch of silicon devices, and far tighter than that produced in University labs Winning approval to develop III-V MOSFETs using silicon foundry tools is not easy, because these materials could linger in equipment and contaminate silicon devices produced in subsequent processing runs. “III-V materials are shallow-level dopants in silicon, so they could introduce threshold voltage shifts and possible reliability problems,” explains Hill. He and his co-workers adjusted foundry processes to both reduce the risk that this would happen and address environmental and safety concerns associated with working with III-Vs. Once this was all in place, they tested the new approach, step by step, using techniques such as total reflection X-ray fluorescence to scrutinize the cleanliness of their tools. “It appears that you can introduce III-Vs, to be run in the same tool set as silicon,” says Hill. However, he stresses that far more wafers must be put through the lines before he can be absolutely certain of this. Although 200 mm silicon substrates are widely used in foundries, the newest fabs are working with 300 mm variants, and 450 mm material is on the horizon. However, Hill believes that it should be fairly straightforward to transfer Sematech’s processes to larger sizes: “The toolset is actually quite similar between 200 mm and 300 mm wafers.” MBE growth To make its III-V-on-silicon MOSFETs, Sematech’sengineers begin by cleaning a 200 mm substrate with awet-etch, loading it into an MBE chamber and subjectingit to an in-situ clean. The choice of MBE tools capable ofhandling such a large substrate is actually quite large,according to Hill, because a platen that accommodates a200 mm substrate is no larger that that holding multiple6-inch or smaller wafers. The MBE tool is loaded with 4° off-cut (100) silicon, specifically selected to reduce the number of anti phase domains that occur when a polar semiconductor is deposited on a non-polar one. A buffer comprising 1μmthick layer of GaAs, plus a 1.05 μm-thick graded layer on InAlAs is grown on the silicon surface (see figure 2). “The buffer technology that we are demonstrating here is designed as a vehicle to allow us to do all the integration and infrastructure development,” says Hill. He does not view this technology as the one that will by used for VLSI     Figure 2. A metamorphic buffer is employed to bridge the gap in atomic lattice constant between silicon and indiumbased III-Vs CMOS integration, which will require a far thinner buffer. On top of the buffer sits a 16 nm-thick In0.53Ga0.47As channel, a 4 nm-thick spacer and a 8 nm-thick barrier that are both made of In0.53Al0.47As, and an In0.53Ga0.47As cap that is 3 nm thick. An Al2O3 and ZrO2 gate is added, before silicon is implanted into the channel and source and drain contacts formed to yield a surface-channel MOSFET (see figure 3).   Figure 3 Sematech’s three terminal MOSFET is made with a process flow that is very similar to that employed for the manufacture of silicon devices   “It’s a three terminal device, not a standard bulk MOSFET,” says Hill, who compares it to a silicon oninsulator MOSFET. One of the strengths of the Sematech device is that its InAlAs buffer has a wider bandgap than the InGaAs layer, which ensures decoupling of the channel from the underlying layers. This leads to immunity from short channel effects, which inhibit channel control by the gate and can include an increase in off-state leakage with increasing drain current and higher junction leakage. Short channel effects can prevent the transistor from being turned off as it is scaled to smaller and smaller dimensions. The MOSFETs produced by Sematech have gate lengths varying from 20 μm to 0.5 μm. The shortest variants have a drive current of 471 μA/μm, a transconductance of 1005 μS/mm and an electron mobility of 1000 cm2/Vs at a sheet doping of 1 x 1013 cm-2. These devices do have one cause for concern, however – a leaky buffer. Measurements between isolated mesa structures indicate that buffer resistance is about 14 kΩ/, which is more than four orders of magnitude lower than that for typical metamorphic InAlAs buffers deposited on GaAs substrates. Transmission electron microscopy and atomic force microscopy measurements on the MOSFETs indicate that the buffer is riddled with defects. Their density in this layer is 109 cm-2, a value high enough to account for the high leakage current in the buffer (see Figure 4).   Figure 4 Transmission electron microscopy image of the cross-section of hetero-buffer. GaAs areal defect density was estimated to be ~1x109 cm-2. The defectivity of the metamorphic buffer is significantly higher   “You can conclude the leakage is going through the buffer for two reasons,” explains Hill. “The off current does not scale with temperature, so it is not an interface state density problem; and the off current does not really scale with gate length, so we know it is a very deep leakage.” Device on-performance is not hampered by the high defect density. According to Hill, that’s because electron mobility is not governed by the mobility of the twodimensional electron gas, which is limited by phonon scattering: “It’s actually [determined] by the surface roughness and interface roughness scattering at the oxide-semiconductor interface.” The road ahead Efforts at improving the buffer are on going. Very recentlySemtech’s engineers slashed the defect density in thislayer, which should drive down the transistor’s leakagecurrent. One of the next goals is to thin the buffer to0.5 μm or less, a step that must be taken to enable thislayer to be used in a successor to silicon CMOS. Torealize this, Sematech’s engineers are looking atalternative material technologies, such as MOCVD growth, selective growth rather than blanket growth, and aspect ratio trapping. Investigating other types of transistor structures is also on the agenda. The type of MOSFET used by Sematech’s engineers up until now was partly chosen because it can be fabricated using a process flow that is very similar to that used to produce silicon transistors. Now the team wants to look at processes for making various types of MOSHEMTs, including those with a recessed gate. “There are many advantages and disadvantages of each technique, and it is not clear to us at this point which one is going to be the winner,” says Hill. “One of our next steps is to build flows with all these different device types and compare them at gate lengths that are similar to where the silicon industry is right now.” In addition to scaling buffer thickness and gate length, Sematech’s engineers will try to reduce contact resistance and junction resistance, and improve the gate stack. It is possible that they will complement this effort with this electron transport device with one based on hole transport, because both types of transistor are needed to build a silicon CMOS successor. “There has been some work published on antimonides with mobilities of about 1000 cm2/Vs, and in some ways an all III-V solution may be advantageous from an integration strategy,” muses Hill. “But germanium technology is more mature.” If all this effort is to lead to III-V MOSFET production in silicon foundries in four or so years time, solving of technical goals must go hand in hand with manufacturing technology developments. According to Hill, it will take a couple of years to order tools, install them and ramp up manufacturing. “That infrastructure development has to be started now to get on the correct time scales.” Hopefully the toolmakers will hear this rallying call, act on it and help III-Vs to play a key role in extending Moore’s Law. © 2011 Angel Business Communications. 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