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Powdec GaN transistor breaks barriers

Dramatically reducing power losses, the device increases break-down voltage and eliminates current collapse.

Powdec and researchers from Sheffield University have succeeded in developing breakthrough high voltage GaN power transistors. This was realised by creating semiconductor hetero-junction structures based on novel principles, which solve the problems of conventional transistors and dramatically improve the transistor performance. In these transistors, current collapse is almost completely eliminated, power losses are reduced and high break-down voltages of more than 1,100 V are realised. These new GaN transistors are suited to be used in a broad range of equipment from inverters in consumer appliances to server power supplies, electric vehicles and industrial motors to lower power use. GaN is a next generation semiconductor that enables power devices to have lower power losses and higher energy efficiency compared to present silicon devices. Together with Powdec’s GaN diodes, these GaN transistors will be core devices enabling an energy efficient, green future. Up until now GaN HFETs with high-voltage, high energy efficiency have been developed, however they suffer from a major problem of current collapse where current decreases and on-resistance increases during operation. To suppress this phenomenon, various techniques have been developed including metal field plates attached to the gate electrode to decrease the electric field and surface passivation to suppress gate leakage. However, improvement in device performance is still not sufficient. In Powdec’s design, instead of a conventional metal field plate, which has hit its limits, a thin film of p-type GaN (p-GaN) is used (Figure 1). Powdec succeeded in realising a polarisation effect in the top and bottom interfaces of the AlGaN layer where equal negative and positive charge is generated, creating a 2 dimensional hole gas (2DHG) and 2 dimensional electron gas (2DEG) at the interfaces (Figure 1). This polarisation effect almost completely suppresses both the current collapse and current leakage at the gate of the HFET. This is a similar effect seen in silicon super junction devices where the entire length of the gate-drain channel is depleted (high resistance), and the electric field is distributed uniformly along the channel, enabling these GaN transistors to sustain high breakdown voltages. This accomplishment will be presented at the 23rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) in May, 2011 at San Diego, USA. Powdec solved the difficult issue of realising a high hole density in collaboration with the University of Sheffield. This allowed a 2DHG of a high hole density of 1.3 x 1013/cm2 to be achieved which Powdec says, for the first time in the world. These transistors with a gate-drain distance of 22mm, in the off-state, sustainable voltages of over 1,100 V are achieved, even without surface passivation. At 1,100 V, drain and gate leakage current is an extremely low 0.3mA/mm and on-resistance is at a “world leading” level of 6 mW/cm2. In a dramatic comparison to conventional HFETs, there is no current collapse at a stress voltage of 350 V (Figure 2). Figure 2. Comparison of current collapse showing virtually zero current collapse for Powdec’s new HFET Going forward, Powdec’s says its breakthrough HFET technology can be easily combined with ‘normally-off’ structures. Powdec now plans to shift growth of the devices to large diameter silicon wafers, with aims to have these energy efficient, high voltage products shipping in volume in 2 to 3 years. To accelerate the market adoption of these innovative, low-power GaN devices, Powdec is actively expanding its partnerships worldwide.

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