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How to grow defect-free GaAs nanowires on silicon

Scientists have found that employing different growth conditions can improve the properties of gallium arsenide nanowires grown on silicon (111) substrates.


If you want to use nanowires in optoelectronic devices, they need to have a pure crystal structure without defects such as twins, phase polytypism and stacking faults.

Now a research group at the Australian National University led by Chennupati Jagadish has developed defect-free GaAs nanowires on silicon substrates by employing special growth processes.

To determine if it was possible to improve nanowire crystal quality, the scientists, led by Jagadish, grew GaAs NWs on Si (111) substrates using 3 different conditions (Fig. 1). By growing GaAs buffer layers to minimise mismatch in lattice constants and thermal coefficients, the researchers achieved straight GaAs NWs when vertically grown on the silicon substrates. 


In collaboration with research groups in the University of Queensland (headed by Jin Zou) and University of Cincinnati, USA (led by Howard Jackson), the scientists then investigated the crystallographic structures and optical properties of the nanowires.

Scanning electron microscopy (SEM), transmission electron microscopy (TEM), and micro- and time resolved-photoluminescence (µ- /TR-PL) measurements were the main analysis techniques used in the study.

Modifying the growth conditions by using two-temperature growth and a rapid growth rate yielded vertical GaAs NWs without surface roughness and structural defects (Fig. 2). 


Figure 2.High resolution-SEM images of (a) Standard GaAs NWs with grooved surface, (b) two-temperature grown GaAs NWs and (c) rapidly grown GaAs NWs showing less tapering without any surface defects, respectively: scale bars represent 200 nm and *Y(vn) means yield of vertical NWs; high resolution-TEM images of (d) the standard NWs having twin defects, (e) the two-temperature grown NWs and (f) the rapidly grown NWs showing pure zinc-blende crystal structure and (g) Cross-sectional TEM image of the standard NWs showing truncated triangular shape. The schematic inset shows the evolution of shape change. All scale bars in insets are 5 nm.

The rapid growth rate method resulted in the highest yield of straight and vertical NWs while the two-temperature growth method yielded NWs with the longest exciton life-time (~ 600 ps) and least tapered shape (Fig. 3), desirable for optoelectronic device applications.



Figure 3 (a) Plot of NW diameter measured at distance from the top of nanowires and illustration of the change in diameter per unit of NW length (ΔD/ΔL) (inset) - all 3 types of GaAs NWs were measured at each 0.5 μm point; (b) Low temperature (15K) TR-PL spectra of three types of NWs.

These results show promise for integrating III-V nanowire optoelectronic devices with silicon based microelectronic devices.

The research group at the Australian National University is now working with the collaborators to investigate multiple applications of GaAs NWs as well as other III-V compound semiconductor nanowires for device applications.

 Details of this research has been published in the paper “Defect-Free GaAs/AlGaAs Core-Shell Nanowires on Si Substrates”, by Jung-Hyun Kang, Qiang Gao, Hannah J. Joyce, Hark Hoe Tan, Chennupati Jagadish, Yong Kim, Yanan Guo, Hongyi Xu, Jin Zou, Melodie A. Fickenscher,Leigh M. Smith,Howard E. Jackson and Jan M. Yarrison-Rice, in Crystal Growth & Design, Dx.doi.org/10.1021/cg2003657.
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