Technical Insight
Research Review: Freestanding a-plane substrate boosts HFET performance
Normally-off GaN HFETs deliver a drain current of 220 mA/mm when built on commercial, native a-plane substrates.
A TEAM of Japanese engineers has smashed the drain current record for an a-plane, normally off HFET by turning to device growth on a freestanding GaN substrate.
Normally off HFETs are far less common than their normally on cousins, which are easier to make and combine high breakdown voltages with high temperature operation and a very high current density. However, in many applications normally off variants delivering the same performance are highly desired, because they cut standby power dissipation, lead to simpler circuits and are essential for making fail-safe circuits.
To make normally off HFETs, researchers tend to turn to non-polar substrates. This allows the density of the two-dimensional electron gas in the channel layer to be controlled by adjusting the donor concentration in the barrier layer.
Some teams, including one from the University of California, Santa Barbara, have used free-standing m-plane substrates to make their normally off HFETs, but this foundation results in high oxygen contamination in the nitride epilayers. Although the high leakage current that results can be tempered with iron doping, this dopant contaminates the channel, reducing drain current and increasing current collapse.
Device performance is also unsatisfactory when HFETs are grown on a-plane GaN on r-plane sapphire, because the transistor is then riddled with dislocations and stacking faults.
However, it is possible to produce HFETs with a high material quality on free-standing a-plane GaN substrates if growth conditions are optimised, says corresponding author Yasuhiro Isobe from Meijo University.
Isobe and his co-workers fabricated their transistors on commercially available a-plane GaN substrates produced by the likes of Kyma Technologies and Sumitomo Electric Industries.
These devices featured an unintentionally doped GaN buffer with a thickness exceeding 7 μm, followed by three Al0.34Ga0.64N layers with thicknesses of 1 nm, 3 nm, and 16 nm. The thinnest and thickest quaternary layers were unintentionally doped, and the 3 nm-thick film sandwiched between them was silicon-doped to a level of 3.5 x 1019cm-3.
According to secondary-ion mass spectrometry, the oxygen level in a-plane GaN layers was below the instrument detection limit of 2 x 1016cm-3.
At a gate-source voltage of 3 V, HFETs fabricated with a 2 μm-wide gate and a source-drain spacing of 8 μm delivered a peak drain current of 220 mA/mm. When this voltage was adjusted to –20 V, leakage current was 8 x 10-6A/mm – a value that the Japanese team says is lower than that for HFETs grown on the widely used c-plane. Transconductance peaked at 56.6 mS/mm, and the threshold voltage was –1.6 V at a drainsource voltage of +8 V.
The team are now trying to fabricate devices with higher levels of performance. They have already had some success, says Isobe, but have also uncovered several issues – a paper detailing all of this will emerge in due course.
Y. Isobe et. al. Appl. Phys. Express 4 064102 (2011)
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