Wrapping a dielectric around an indium gallium arsenide channel could hold the key to scaling ICs beyond the 14 nm node.

 Researchers from Purdue and Harvard are claiming to have made the first three-dimensional III-V transistors with techniques that are similar to those for making ICs in foundries.

The architecture of their InGaAs transistor, which has just been detailed at the International Electron Devices Meeting, mirrors that of 22 nm-node silicon MOSFETs that are now rolling off Intel’s production line.

The similarity of these two transistors makes the InGaAs MOSFET a strong contender for IC manufacture beyond the 14 nm node.  The road map for CMOS predicts that alternatives to silicon will be needed at these very small length scales, and III-Vs are widely tipped to take over.

 



 (a) An SEM image of the InGaAs nanowire test structures after the release process (b) Cross-sectional TEM of the InGaAs nanowires wrapped in the dielectric (c) A finished InGaAs gate-all-around FET with 4 fingers

The Purdue-Harvard team is by no means the first to make a three-dimensional III-V transistor; many other research groups have already achieved that feat, but in every case they have formed nanowire structures with a ‘bottom-up’ approach.

“Industry has interest in that work, but not strong interest,” says Peide Ye, leader of III-V MOSFET research at Purdue University. He points out that most of the wires that are made with bottom-up techniques are grown randomly. “It is difficult to put these transistors where you want, and connect them together to form a circuit.”

According to Ye, the silicon industry is far more interested in developments involving top-down approaches. That includes the lithography, dry/wet etching and atomic layer deposition (ALD) processes that he and his co-workers have used to fabricate their MOSFET.

Three-dimensional transistors benefit from wrapping of the dielectric around the channel to minimise so-called ‘short-channel effects’. These generally become worse and worse as the transistor’s feature sizes are scaled down, because the dielectric used for making the gate must be thinner.

When the silicon industry reached the 45 nm node it departed from the traditional silicon dioxide gate, using hafnium dioxide instead to temper short-channel effects. At the 22 nm node these effects are even more severe, so chipmakers are turning to three-dimensional transistors to address this issue. These three-dimensional devices enshroud the channel with a dielectric to control current flow.

“It’s the same story happening with III-Vs, because the device physics in principle is the same,” says Ye.

His student, Jiangjiang Gu, took two years to figure out how to make a gate-all-around III-V MOSFET. He focused on finding a simple approach to making this device that would employ processes suitable for use in a silicon foundry.

Device fabrication begins with MBE growth of a 30 nm-thick InGaAs layer on p-doped InP. Implanting silicon ions creates source and drain regions, and a lithographic process forms nanowire InGaAs channels.

Anisotropic wet etching with hydrochloric acid removes InP, including that beneath the InGaAs channel. This is only successful when the channel is aligned along the [010] direction, an orientation that produces undercut etching.

ALD, which is a “super-conformal” process, wraps the channel in a 10 nm-thick coating of Al2O3 and then surrounds it with a WN gate. A second lithographic step selectively removes part of the WN layer, allowing contacts to be made to the source and drain regions.



  Three-dimensional III-V MOSFETs are produced by: Deposition of an InGaAs layer on an InP substrate by MOCVD; silicon ion implantation to form source and drain regions; creation of a nano-bridge by etching; ALD to wrap a dielectric around the channel; and gate etch.

The MOSFETs that result have been produced with either 1, 4, 9 or 19 InGaAs nanowire channels. Using multiple wires allows the researchers to not only study their uniformity, but also increase total current delivery for the device.

High values for transconductance and drain current showcase the promise of these devices for forming high-speed logic circuits.

Devices with a 50 nm gate length have a transconductance of 710 μS/μm, revealing that scaling to small dimensions is not detrimental to transistor performance. “With our planar devices, after 150 nm you are out of control,” says Ye.

 



 The gate-all-around FETs set a new benchmark for transconductance at short gate lengths, indicating their potential for making high-speed logic circuits

Drain current, which has been normalised by the perimeter of the wire to allow fair comparison with results for planar structures, peaks at 1.17 mA/mm for a ‘hero’ device. “That’s a very high current – higher than the III-V bottom-up work.”

Typical values for sub-threshold swing and drain-induced barrier lowering for a device with a 50 nm gate length are 150 mV/dec and 210 mV/V, respectively.

The values are quite high, and Ye admits that there is a lot of work to do in this area: “The interface is difficult and there is still a lot of engineering work to be done. The sub-threshold slope needs to come down to 65-70.”

If these III-V devices are to be used in future ICs beyond the 14 nm node, they will have to be formed on silicon substrates. “That’s very challenging,” admits Ye. His work doesn’t focus on that, but he points out that there is good progress in this direction by the likes of imec, SEMATECH, and the partnership of Intel and IQE.