III-Vs and the silicon roadmap

Time and time again, critics have claimed that there will soon come an end to the shrinking of silicon transistors to smaller dimensions. Some have argued that photo-lithography cannot extend beyond optical wavelengths – but tools have been built that can do just that; others have warned that electrons cannot zip about fast enough when transistors reach the nanoscale – but adding a little strain into the material has put that issue to bed; while others have pointed out that high leakage currents will put an end to device scaling – but this issue has not been a show-stopper, thanks to a switch from silicon dioxide to high-k dielectrics, such as hafnium dioxide. Today, claims that the days of the silicon transistor are numbered are still being made – and there’s a good chance that this time the critics could well be right. That’s because this belief is not just held by those outside the silicon industry, but also some within it: Alternatives to silicon are now on the International Technology Roadmap for Semiconductors (ITRS), with III-Vs and germanium predicted to make an impact at the 11 nm node that could be rolled out in 2015. Iain Thayne from the University of Glasgow, UK, explained the reason for the potential invasion of these new materials into silicon lines at the recent CS Europe conference in Frankfurt, Germany. Thayne, whose efforts at developing III-V transistors initially focused on RF and millimetre-wave front-end applications, argued that compound semiconductors must be introduced to maintain performance as dimensions are reduced. “Increasing the density of transistors in silicon leads to heating, which will soon approach an air-conditioning limit,” said Thayne. He explained that preventing over-heating in the circuits that will be built with tomorrow’s transistors requires a reduction in the voltage of the power supply, but no compromise in performance. The only way to satisfy these conditions is to replace silicon transistors with those based on III-Vs and germanium. He also pointed out that scaling efforts are focused on increasing the density of transistors. Although every new node has a shorter gate length, it also has a reduction in gate pitch, which is scaled even more aggressively (see Figure 1). Figure 1. According to the ITRS roadmap, between 2011 and 2024 reductions in gate pitch will be more rapid than those in gate length - Image reproduced courtesy of IEEE Spectrum Sceptics within the silicon industry have argued that III-Vs will never be suitable for logic circuits, because the drive currents produced by this class of transistor are not high enough, due to the low densities of states associated with compound semiconductors. But Thayne’s colleague Asen Asenov has spotted fundamental flaws in this argument: Although the low density of states in III-Vs leads to a lower effective capacitance, these materials combine a high mobility with a low mass, resulting in the injection of carriers with high velocities and increased ‘ballisticity’. What’s more, the lower density of states means that carriers are injected with a higher velocity, thanks to their higher energy; and due to superior mobility, these materials can trim access resistance and thereby boost the efficiency of gate modulation. Material attributes To optimise III-V MOSFETs, developers must select a material that combines a high carrier velocity with the potential to yield a device with a low operating voltage. According to Thayne, as gate pitch decreases from 75 nm to 15 nm (the value expected in 2024), channel concentration may decrease from 8.5 x 1012 cm-2 to 5.1 x 1012 cm-2 while the carrier velocity will increase from 1.3 x 105 ms-1 to 3.5 x 105 ms-1. The most promising materials for meeting those requirements are alloys of InGaAs, and work from MIT suggests that In0.7Ga0.3As channels can produce injection velocities above 3 x 105 ms-1 at gate lengths below 20 nm. Thayne discussed additional requirements for the introduction of III-V MOSFETs for logic applications. He said that transistors will need to have a sub-threshold swing of 75 mV/decade so that they could be turned-off easily, and they will probably need to be built with a non-planar architecture, such as the ‘Ivy Gate’ tri-gate structure employed by Intel for the manufacture of transistors at the 22 nm node. In addition, due to scaling, source and drain dimensions will have to be just a few nanometres, which could lead to an unwanted hike in contact resistance. The Glasgow team, which has been involved in both the European Dual Logic programme and efforts led by the Semiconductor Research Corporation Non-Classical CMOS Research Center, has focused its efforts in three directions: Gate stack improvements, resolving issues related to the scaling of source and drain contacts, and the development of silicon compatible process flows for III-V MOSFETs. Efforts have centred on a flatband architecture MOSFET (see Figure 2). This is similar to a HEMT, according to Thayne, because there is delta-doping in a high bandgap material, leading to the transfer of electrons to a low bandgap channel where they create a high-mobility, two-dimensional electron gas. If a high workfunction gate metal is formed on top of the dielectric, depletion occurs, driving the device into an off-state at zero bias. Forward biasing of the gate repopulates the channel with carriers. This MOSFET architecture is claimed to have two key strengths: Immunity to short-channel effects, due to a high bandgap lower barrier; and high mobility, thanks to a combination of no doping in the channel, low interface roughness scattering and a low resistance of the source and drain extension access regions. When the team started developing III-V MOSFETs at the beginning of the previous decade, efforts were partly devoted to establishing a good gate stack. Initially they employed a Veeco Gen III dual chamber MBE system to grow III-V layers by MBE on a semi-insulating GaAs substrate, before transferring the sample under vacuum to a second chamber, where they added a Ga20 template and a GdGaO layer. The flatband III-V MOSFETs fabricated from these wafers produced mobilities in excess of 5000 cm2 V-1s-1 at sheet carrier densities above 2 x 1012 cm-2, and transistors with a 1 μm gate length had a transconductance of 357 μS/μm and a sub-threshold swing of 68 mV/decade. To increase injection velocity, the researchers switched to In0.53Ga0.47As channels and Al2O3 dielectrics, which were deposited by a 60-cycle atomic layer deposition process. The benefits of this new structure included gains in mobility – at an electron density of 2 x 1012 cm-2 mobility topped 6000 cm2 V-1s-1. For surface-channel transistors with a 1 μm gate and a 2.5 nm-thick Al2O3 dielectric, transconductance hit 432 μS/μm, but the subthreshold swing reached 150 mV/decade. Intel’s move from planar transistors to three-dimensional varaints points the way to production of non-planar devices, which will not have pristine interfaces. To consider the implications of this trend, Thayne, in partnership with Paul McIntyre at Stanford and Paul Hurley at the Tyndall Institute, has looked at the impact of various treatments of transistor performance. The team compared three wafers. Two of them were removed from the MBE chamber after the growth of III-V materials: A gate dielectric was added to one wafer without any intermediate surface treatment, so air-exposed oxides were likely to be present in the dielectric-semiconductor interface; and a optimised sulphidation treatment was applied to the other prior to deposition of the high-k dielectric. The third wafer had as arsenic cap deposited in the MBE chamber to prevent oxidation in air. This cap was removed in the atomic layer deposition tool at Stanford, enabling the gate deposition on a pristine surface. Measurements of the mobility of MOSFETs made from these wafers reveals that it is possible to produce interfaces as good as those on pristine surfaces if a sulphidation process is performed (see Figure 3). Figure 3. A sulphidation process developed by researchers at the Tyndall Institute can offset most of the degradation in mobility resulting from the removal of an arsenic cap. This is a promising result for non-planar transistors,which will not have pristine interfaces The second issue that Thayne and his co-workers have investigated is the fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024, source and drain contacts must be trimmed from 21 nm to 2 nm, while source and drain resistances are cut from 160 Ωμm to 110 Ωμm. ‘Traditional’ approaches will not succeed – experiments and simulations reveal that contact resistance rises rapidly when the contact size enters the nanoscale. Several groups have recently developed different approaches for overcoming this problem, including that from Glasgow, which has turned to NiInAs to fabricate an ultra-low resistance, shallow, metallic source-drain. According to Thayne, this is the first source-drain technology that can meet the most aggressive ITRS specification for the 12 nm technology node, which corresponds to a gate pitch of 27 nm. The third strand of research at the Nanoelectronics Research Centre is the development of approaches for forming fully selfaligned III-V MOSFETs with silicon compatible process flows. The team has pioneered two different designs: ‘Gate first’ and ‘replacement gate’ architectures. The former has been used to form In0.3Ga0.7As flatband MOSFETs with a GaO/GaGdO dielectric stack and a 100 nm gate length. These transistors exhibit a peak drain current of 250 μA/μm, transconductance of 150 μS/μm and a sub-threshold swing of 150 mV/decade. Sub-threshold swing falls to 130 mV/decade with the replacement gate architecture, which has a modest on-state performance due to a very high access resistance of 18 kΩμm. This issue can be addressed by improving the source drain anneal, which is needed to supress material diffusion in very small devices. Into the third dimension One team that is following Intel’s lead and taking III-V MOSFETs into the third-dimension is Peide Ye’s group from Purdue University. Ye detailed an evolution path for FETs, which begins with a bulk III-V planar architecture and ends with a III-V gate-allaround HFET (see Figure 4). His team have recently fabricated the latter structure, which is built on InP substrates and features a p-doped InGaAs channel, or multiple channels, wrapped in a 10 nm-thick layer of Al2O3 and a thicker layer of WN (see Figure 5 for details). Devices with 4 parallel channels, a 50 nm gate length and a 30 nm fin width produce a very low gate leakage, a peak current of 1170 μA/μm and a sub-threshold swing of 150 mV/decade. Figure 4. According to Peide Ye from Purdue University, III-V MOSFETs have evolved from planar structures to those that wrap a dielectric right around the channel Figure 5. Peide Ye’s group at Purdue University have pioneered the III-V gate-all-around FET. Transistors that they have built so far feature a gate length of 50-120 nm, a fin width of either 30 nm or 50 nm, and 1, 4, 9 or 19 parallel wires with a length of 150-200 nm and an Al2O3 dielectric with a thickness of 10 nm The second issue that Thayne and his co-workers have investigated is the fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024 These devices have several promising attributes for making an impact on the ITRS roadmap. Reductions in gate length result in an increase in current and transconductance, and the transistors appear to be immune from short channel effects. What’s more, reductions in the dimensions of the nanowire channels lead to a hike in current flow, thanks to quantum confinement. Recently, Ye has had a paper accepted for publication in Electronics Letters that details these findings. He and his team found that the current increased by 40 percent when nanowire widths were reduced from 50 nm to 30 nm, while mobility and transconductance increased by 34 percent and just over 20 percent, respectively. To understand why thinning of the nanowires has lead to an increase in current – this is the opposite of what one would expect – the team simulated device behaviour using Sentaurus Device, a tool made by Synopsys. Simulations revealed that nanowires operate in the volume inversion regime, which means that the electron density reduces at the edges of the nanowire and increases in its inner region. Electrons can then, on average, travel faster through the channel because it is increasingly likely that these chage carriers are away from the interface, where scattering impedes progress. Simulations suggest that the proportion of electrons in the middle of the wire increases as its dimensions are reduced, with a very promising electron density profile reached for a width of 10 nm. Building on silicon If compound semiconductor MOSFETs are to move into production, they must be made on large diameter silicon substrates. Forming high quality germanium and III-V transistors on silicon is tricky, due to differences in lattice constants and crystal structures, but progress in this direction is being made by Matty Caymax’s group at imec, Belgium. At CS Europe Caymax detailed efforts to form high-quality germanium and III-V devices on silicon, the latter achieved using trenches with a cup-shaped bottom (more details can be found at imec prepares the ground for III-V transistors on silicon, Compound Semiconductor March 2011 p.12). This approach (see Figure 6) eliminates anti-phase domains that lead to device shorting. “The best result that we have right now is a defect density of 2 x 108 cm-2,” said Caymax. “This is not sufficient – we have to work to get a lower dislocation density.” Figure 6. Researchers at imec are developing processes to unite germanium and III-V transistors on a silicon substrate Transistors made recently suffer from a high junction leakage. To investigate the origin of this leakage, the team have carried out atom probe tomography, a technique that has revealed that some atoms are located in places where they should not be: Some germanium is found in InP, and some indium and phosphorous atoms are located in germanium and the underlying silicon substrate. Caymax’s team, like those headed by Ye and Thayne, still has work to do to help III-Vs to make an impact in future logic applications. But the results to date are promising, showing ways to overcome many tough hurdles, and it seems that when silicon CMOS finally runs out of steam in a few years’ time, compound semiconductors will be there to pick up the pieces.