GaN-on-silicon products will become far more competitive when processing is carried out at fully depreciated 200 mm silicon fabs. This requires the use of very flat wafers, which can be formed through the introduction of rare oxide epi-layers that can also enhance the performance of LEDs, transistors and solar cells, say Michael Lebby, Andrew Clark and Guoying Ding from Translucent.

To fulfil the unrelenting drive for cheaper consumer products, scientists need to develop and introduce new materials that can slash the cost of semiconductor devices. This is especially true for GaN-based technologies – these can form a wide range of devices at costs that will get more and more competitive when epitaxial growth is performed on large silicon wafers. Such devices promise to spur the widespread adoption of LED-based lighting, aid the penetration of GaN-based transistors in the power electronics industry, and help the growth of the multi-junction solar cell market that is traditionally making products for satellites, but is now complementing this with devices for terrestrial concentrating photovoltaic systems. 

At Translucent of Palo Alto, CA, we are playing a key role in the development of engineered, silicon-based substrates for the manufacture of GaN products. These large-diameter ‘on-silicon’ wafer platforms, which provide a strong foundation for GaN and germanium epitaxial growth, are by no means the only engineered platforms that exist. However, they have a major advantage over many of them, thanks to their silicon base: They can be processed in the high-volume, highly automated 150 mm and 200 mm silicon fabs dotted around the world. This means that they promise to trim the price of electronic devices based on GaN-on-silicon and germanium-on-silicon, which tend to be made on smaller substrates.

In addition, they can be an attractive alternative to sapphire for the growth of LEDs. The GaN LED industry is migrating from 2-inch, 4-inch and 150 mm platforms used today to 200 mm and beyond.

The appeal of our engineered substrates is not limited to their competitive price – they also simplify epitaxy and wafer fab processing. Given the standard tool kits in these large silicon fabs, thin flat wafers are a pre-requisite for automatic batch loading.

One of the first demands from the silicon community, when faced with the request to process wafers featuring GaN or germanium is essentially: “We need flat wafers folks. We are not interested in the quality of your GaN, but if you want us to process them – they had better be flat.”

Silicon is certainly not the only foundation looking to impact these fast growth markets; scaling to 200 mm has been demonstrated in both sapphire and germanium.

However, both these alternatives suffer from cost, fragility, yield and thickness issues, which don’t plague epitaxial structures formed with our engineered substrates.

Rare earth oxides

Our engineered ‘on-silicon’ templates are formed using crystalline rare earth oxides (REOs). Working with this family of materials is beneficial for many reasons: REOs permit strain engineering; they can scale to 200 mm; they enable field screening in FETs, if this wide bandgap oxide is inserted between GaN and silicon; and if they are stacked with silicon, they can form a distributed Bragg reflector that can reflect the emission produced by the LED away from the silicon substrate, which would otherwise absorb this light. In addition, REOs have the potential to form a high-k gate dielectric through in-situ deposition without breaking vacuum (note that this feature is not discussed in this article). 

We have successfully developed epitaxial growth processes for a range of crystalline REOs on silicon (111), including Gd2O3and Er2O3.  The process has already been scaled from 50 mm to 200 mm, and there is the opportunity to migrate to larger platforms in the future.

The epitaxial deposition process for forming GaN materials employs custom-designed, solid-source epitaxy reactors. These are based in part on the principles of MBE, but modified to handle oxides and silicon fab cluster tools. We have recently completed the design of a 200 mm epitaxial reactor that can handle a single 200 mm wafer. This will complement our growing range of multi-wafer tools: This year we are implementing multi-wafer tools for a capacity of 7 x 150 mm or 3 x 200 mm wafers.

A perfect match

One of the great assets of crystalline oxides is the value of their lattice spacing, which is almost exactly twice that of silicon. Within the rare earth series (lanthanides) of the periodic table there are a number of elements with slightly different-sized cells.  The most notable of these are oxides of: ytterbium, erbium, gadolinium, neodymium and lanthanum.

We have grown all of these oxides, before studying their properties to determine whether they can support alternative material templates.  When comparing lattice dimensions to other semiconductors, such as GaN and even germanium, it is clear that these oxides can be used to engineer silicon wafers for use as epitaxial templates (see Figures 1 and 2; the former provides a comparison of the relative surface unit cells of (0001) GaN, (111) silicon, germanium and 1/2 unit cell (111) REOs.)



Figure 1. Comparison of surface unit cells (decreasing left to right)

 

‘Tunability’ of various rare earth binary and ternary oxide alloys are demonstrated in X-ray scans (see Figure 2). If there is a requirement for a lattice coincident oxide, also known as a matched oxide, Gd2O3is a good candidate because its lattice constant is very close to twice the lattice constant of silicon, 10.86 Å. But if the preference is for a little tensile strain, this oxide can be graded with Er2O3to form a range of ternary alloys with lattice spacing ranging from 10.81 Å to 10.55 Å. And if compression is desired, it is possible to use ternary alloys constructed from Er2O3and Nd2O3(see Figure 2). To date the predominant use of this alloy has been as a template for SiGe growth - the plot in Figure 2 shows an overlay of 10 percent steps in the composition of SiGe with corresponding data from a matched ternary oxide. 



Figure2. X-ray diffraction scans for various rare earth binary and ternary oxide alloys.

It is this ability to set a final oxide lattice spacing that is the key to strain engineering. However, with any template engineering another criteriion must be satisfied: The material must withstand all upstream thermal budgets. Fortunately, crystalline REOs are very stable, as revealed by X-ray patterns that are repeatable when the material is subjected to temperature cycling up to 1100 °C. In addition, X-ray spectra show that it is possible to form repeatable material compositions over the course of a year.

Growth of GaN-on-silicon is known to be difficult. This is primarily due to the large mismatches in lattice constants and coefficients of thermal expansion (CTE) between GaN and silicon. Left unchecked, this can cause wafers to bow and even crack.

To address this issue, we have adopted a strain management strategy based on two approaches: Lattice engineering via REO composition and grading as previously discussed, and pre-straining of wafers using oxides of varying thicknesses. The results of the second approach, which produces a greater strain effect, are detailed in the remainder of this article. Taking this tack makes it possible to apply differing amounts of strain compensation to 100 mm silicon wafers by varying the thickness of the REO and the GaN layer (see Figure 3). Repeating these experiments revealed that our strain engineering technique can be scaled to larger format silicon wafers.



Figure3. Ex-situ bow data for oxide and oxide + GaN of 100mm.

Reflected glory

The high crystalline quality of REOs makes them an ideal template for subsequent epitaxy. For example, it is possible to deposit, in situ, a distributed Bragg reflector (DBR) by pairing the oxide with another material with a different refractive index.  At 450 nm, the difference in refractive index between silicon and Gd2O3is 2.2. This difference is far larger than that for AlN-GaN materials used to date in some LEDs, implying that DBRs incorporating Gd2O3are much more efficient.

This promise is borne out in practice. Measurements show that a DBR with a peak reflectivity exceeding 85 percent can be built with a four-period mirror made from Gd2O3and silicon; if III-N materials are used instead, ten periods are required to hit this reflectivity (see Figure 4). What’s more, the combination of Gd2O3and silicon increases the width of the stopband. Using an identical number of mirror pairs, the stopband for Gd2O3-and-silicon is three times that for the III-Ns (181 nm, compared to just 61 nm).



Figure 4. (a) Refractive index data (top left); (b) peak reflectivity verses layer pairs (top right); (c) Reflectivity verses wavelength showing increased stopband width for oxide-silicon DBR (bottom)

A fully embedded DBR mirror on a silicon wafer enables a new level of flexibility in the fabrication and processing of LEDs. Armed with this composite platform, a complete GaN/InGaN LED device can be directly grown without the need for substrate removal, wafer bonding, and the associated fabrication steps of removing silicon. The high reflectivity of the DBR prevents light emitted by the LED from being absorbed in the silicon substrate.



Figure 5. (a) Transmission electron microscopy images of the REO-silicon stack, spectral data for DBR, (top left to right); (b) Wafer maps for centre wavelength, stop bandwidth and peak reflectivity from a 100mm diameter wafer (bottom, left to right).

Although many manufacturers have demonstrated substrate removal techniques, this process gets more complex and its cost becomes prohibitive as wafers scale to 200 mm and beyond. It seems that the concept of ‘chip and ship’ is rising in importance as the LED industry gains in maturity and volume through applications such as solid-state lighting. We have been able to construct high-quality, in situ embedded DBR mirrors on wafers with diameters of 50, 100, 150 and 200 mm. Alternating layers of epitaxially grown Gd2O3and silicon have combined to form a DBR wafer with a peak reflectivity of 82 percent at 450 nm (see F. Erdem Arkun et al. Phys. Status Solidi C 9814 (2012) for details of the growth of REO-based mirrors and their integration with GaN). Depending on design, stop bandwidths are typically in the range 60-80 nm and are highly suited to handling LEDs with light emission in the 440-470 nm range.

Scaling to large sizes

The promise of wafer processing at fully depreciated silicon fabs is a key value proposition for GaN-on-silicon technology. To spur this on, processes must be developed for manufacturing 200 mm flat wafers that can quickly win acceptance within the mature silicon industry. 

What is meant by flat? Wafer bow must be below 100 µm over a 200 mm wafer.  To meet this target, strain management must be accomplished as part of the epitaxy stack. This management must not be limited to single oxide layers, but must include more complex structures, such as DBR mirrors that include silicon layers. 

Our efforts in this direction have included the growth of single layers of Gd2O3with thicknesses of 0.1 µm-0.5 µm on 200 mm silicon (111) wafers. Measurements of bow were performed during the growth, before the wafers were taken out of the reactor and evaluated again.

Measurements on wafers with 300 nm and 500 nm oxides show that this layer induces convex bow (see Figure 6). This bow increases as more of the REO is deposited, revealing that it is possible to control the level of compressive strain in an oxide-based template by selecting the thickness of the oxide.



Figure 6. In-situ bow data from 300nm REO thickness (top); and (b) in-situ bow data for 500 nm REO (bottom). Note graph are to scale.



Figure 7. In-situ bow measurements of a three-pair REO- and silicon-based mirror on a 200 mm silicon (111) wafer. Arrows indicate the compressive strain induced by each oxide layer as it grown.

Growth of oxide-based DBRs on 200 mm wafers produced similar results. During the deposition of alternating oxide and silicon layers with thicknesses of λ/4 and 3λ/4, the addition of every oxide layer imparts compressive strain to the multi-layer stack (see the arrows in figure 7). Note that this DBR is not fully optimized, due to a reduction in total oxide thickness. We have found that the silicon layers within the DBR result in some tensile strain, due to the different growth temperatures used in the multilayer structure. However, overall the direction is towards the desired compressive strain.

Subsequent growth of GaN confirms this – the final centre-to-edge bow for this 200 mm diameter wafer was 54 µm concave (figure 8), a figure that satisfies silicon industry specifications for this size wafer. Complete strain management is possible, but this requires additional oxides.



Figure 8. Ex-situ bow measurements ofa three-pair DBR mirrors after growth of bulk GaN showing center to edge wafer bow of 54µm

Nonetheless, given that the silicon substrate was only 750 µm in thickness, this is a very encouraging result and confirms that REO templates offer a successful route to strain engineered GaN-on-silicon.

The deployment of multiple layers of oxides for strain management and improved device performance is not limited to LEDs; this form of architecture also promises to pay dividends in GaN-on-silicon power devices (see Figure 9 for an example of both structures). REOs combine a wide bandgap with a high value of permittivity – it is greater than 12 – and may allow an in-situ gate oxide to be deposited on top of a GaN FET stack witout breaking vacuum.



Figure 9. Oxide-based template engineering for strain, optical and electrical enhancement of silicon based III-N wafers.

Capacitance-voltage measurements show minimal hysteresis, while breakdown testing reveals a consistent breakdown voltage of 4 MV/cm. It’s clear from these results with simplified LED and transistor structures that REOs offer great promise to improve device performance and trim manufacturing costs. The range of oxides is considerable. This means that there are many avenues – some still to be explored – for taking LEDs, transistors and solar cells to new levels of affordability and performance.