Technical Insight
Singapore MIT Alliance focuses on wafer-scale integration
Singapore and MIT partners have joined forces with Global Foundries to drive III-V CMOS integration forward. Compound Semiconductor talks to Professor Eugene Fitzgerald from MIT to find out more.
The LEES project aims to develop novel materials compounds and integrated circuits on 200mm silicon wafers. Credit: Aixtron
US-based Massachusetts Institute of Technology and the National Research Foundation of Singapore have joined forces to drive wafer-scale integration of III-V-on-silicon forward.
The Singapore and MIT research centre, known as the Singapore MIT Alliance for Research and Technology (SMART), launched the US$35 million Low Energy Electronics Systems (LEES) project in January this year.
Led by Eugene Fitzgerald from MIT's Department of Materials Science and Engineering and Soon Yoon, from the Electrical and Electronic Engineering Department at Nanyang Technological University, Singapore, a team of researchers from both organisations aims to develop novel materials, process technologies and integrated circuits on 200 mm CMOS-compatible silicon wafers.
“A lot of III-V device interest for CMOS is being pursued in research labs, but we're not focusing on that. We want to take CMOS as it is and take III-V semiconductors, bring them together and make a silicon system that has great value,” says Fitzgerald. “We're looking for new applications and new end-markets.”
The team is currently building a fabrication plant in Singapore, which is due to open in January, next year. As Fitzgerald's colleague, Yoon points out, the facility will comprise a clean room with epitaxial tools, particularly MOCVD, so researchers can work on GaN, GaAs and InP deposition on silicon substrates. Indeed, the researchers placed an order for two Aixtron CRIUS 1X200mm systems earlier this year.
Aixtron systems will be used as part of the project from the fourth quarter of 2012. Credit:Aixtron
Crucially, the researchers are also working with Singapore-based Global Foundries, the world's second largest independent semiconductor foundry,to trial their III-V semiconductors on CMOS processes.
“We've signed an agreement with Global Foundries to run our technology at the foundry,” says Yoon. “Researchers at our LEES laboratory will be working on the III-V materials, with these materials then being moved out of our clean room and into the foundry for CMOS processing. The wafers will then come back to us for the final layers, at which point most of the electronic circuits on the silicon side will have been processed.”
As Fitzgerald emphasises, the LEES laboratory is being built to complement manufacturing 200 mm silicon wafer plants. “By building this missing piece we can develop device models based on III-V semiconductors and plug them into CMOS designs. This will allow designers to create new integrated circuits,” he adds.
However, materials research remains crucial to the project, and the researchers will be using well-established techniques, including aspect-ratio trapping and metamorphic buffer layers, to minimise the lattice mismatches and strain between III-V materials and silicon substrates.
Aspect-ratio trapping uses high aspect ratio sub-micron trenches to trap threading dislocations and reduce the dislocation density of the lattice mismatched material grown on silicon. The hetero-integration technique has already been used to integrate germanium and III-V devices on silicon including GaAs MOSFETs, lasers and tunnel diodes.
Meanwhile, metamorphic buffer layers are deposited to absorb the strain between lattice mismatched layers, prevent the propagation of dislocations and ensure the quality of the device active layers. Researchers worldwide have developed myriad buffer layer designs to say grow InP on GaAs and SiGe on silicon.
With this in mind, Fitzgerald is now looking forward to having a wealth of different methods to produce quality materials for the desired circuit. “In some cases you might want to use small-area growth or aspect-ratio trapping, while metamorphic buffers can be used to make entire substrates suitable for device [growth],” he says.
But as he points out, his team will be using combinations of these methods to achieve the defect density required for different devices, from transistors, LEDs and lasers to integrated photovoltaics and micro-batteries.
“It all comes down to what defect density you need to achieve the desired performance and reliability in a device,” he adds. “Take reliability, this can only really be determined when you are building your circuits, as that's when you can test what defect density is needed from a circuit. So in Singapore we will be working at this level to really find out what the missing pieces are to build the desired circuit.”
