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Terabit interconnect project combines III-Vs with silicon

The three year project announced by imec, will combine III-V high speed VCSELs with various silicon components to allow new functionalities such as wavelength multiplexing
MIRAGE, a new EU FP7 project, was recently launched with the goal to develop next-generation optical interconnect technology for terabit data links.

The project that focuses on optical rack-to-rack and board-to-board interconnects is scheduled to run for three years and brings together seven leading academic and industrial partners in the optical value chain.

Along with imec, the project participants are the National Technical University of Athens (Greece), Austriamicrosystems AG (Austria), OptoScribe Ltd. (UK), Technische Universität München (Germany), Aristotle University of Thessaloniki (Greece) and AMO GmbH (Germany).

Today the internet is morphing into a content-centric network with billions of users demanding ubiquitous, instant access to vast amounts of data. In this new networking paradigm, the hot spots are the data centres, where the bulk of the information is residing.

These data centres may consist of hundreds or even thousands of servers interconnected with each other. The content providers are in a constant race to increase this interconnection speed to improve the delivery of the data to the end user.

It is MIRAGE’s ambition to increase the optical interconnect speed, which currently tops at around 140Gb/s per link, and bring it to the terabit realm. To do so, the program will tackle the issues that still have to be solved to develop technology suitable for commercial adoption.

The project will look into a number of things. These include high speed III-V VCSELs, low-energy electronic drivers and a flexible motherboard technology that allow new functionalities such as wavelength multiplexing. MIRAGE will also explore multi-level modulation and multicore fibre coupling, and ways to introduce new degrees of parallelisation into the optical interconnects.

What's more, the project partners will develop new assembly processes based on 3D-integration of electronic and optical components to effectively blend silicon, glass and III-V photonic elements with CMOS electronic drivers. 

In this project, imec’s associated lab at Ghent University will develop the dedicated high-speed low-power VCSEL driver array and the transimpedance amplifier array. In these IC designs, imec will focus on the close integration and matching of the drivers with the corresponding VCSEL/photodiode arrays. The team will co-optimise the electronic circuits, parasitic elements, interconnects and optical-electronic-optical component parameters to take advantage of the various new technologies developed by the MIRAGE consortium.

Imec will also develop an innovative methodology to simplify bonding the MIRAGE active add-ons to the silicon platform. For VCSEL and photodiode bonding, in particular, tight alignment tolerances usually require costly equipment whereas the large distance between VCSELs and waveguides necessitates the use of microlenses to account for the beam divergence.

MIRAGE will confront these costs with a self-alignment assembly process based on microbumps.

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