The most promising building blocks for the 11 nm node are the pairing of III-V and germanium transistors. Device development is still in its infancy, but research presented at IEDM 2012 indicates that significant progress is being made. Richard Stevenson reports.

Silicon is running out of steam. Using this material to maintain the march of Moore’s law is getting more and more challenging, and engineers are now close to exhausting their list of options for realizing device improvements that must come with every round of scaling. They have already turned to new, novel oxides to stop leakage currents from escalating; they have introduced strain to zip electrons and holes through the channels at higher speeds; and most recently, they have re-written the rulebook for transistor design and started to manufacture a three-dimensional MOSFET, known as either a Tri-Gate device or a FinFET, in order to enhance electrostatic control. Next on the agenda is to scale these 22 nm devices to the 16 nm node, but beyond that, a more radical approach is needed to maintain the performance improvements wrought from the introduction of every new node, such as a 20 percent power reduction per transistor.

Trimming power consumption, which prevents IC overheating, is not a trivial task. That’s because power consumption of the IC depends on several factors. At lengths scales of 90 nm and above, most losses result from dynamic power consumption, which is proportional to the clock frequency and the square of the transistor’s operating voltage. But at the smaller nodes, leakage currents dominate. These are proportional to the operating voltage, and can result from leakage at the gate, the junction and the source-drain region.

Reducing the operating voltage is the best way to maintain Moore’s law to the 11 nm node and beyond, because this minimises dynamic power consumption and leakage currents. Cutting the operating voltage of silicon transistors, which now operate at about 1.1 V, is very tricky, but big reductions are possible by introducing new materials with higher mobilities. The most promising ones are listed in the International Technology Roadmap for Semiconductors (ITRS). Turning to the combination of III-Vs for the electron channel and germanium for the hole channel is seen as the most likely way forward, because this pair of materials combine high mobilities with a significant level of maturity.

However, before these materials can make an impact at the 11 nm node, which will be introduced in foundries in 2018, several questions must be answered: Can III-V and germanium transistors work well at this length scale? What stack of materials should be used to insulate the gate from the channel? What transistor architecture should be adopted? And how can these transistors be formed on 300 mm silicon, which is the only substrate that can be considered, because billions of dollars of foundry equipment has been built around it.

At the International Electron Devices Meeting (IEDM) in San Francisco that was held from 10-12 December 2012 engineers from a variety of backgrounds offered answers to all these questions. Contributions from delegates included: Promising device results on InGaAs MOSFETs with a gate length of just 22 nm; new architectures for boosting drive current; improved gate dielectrics for electron- and hole-conducting channels; and wafer-bonding technologies for forming III-V transistors on a silicon substrate.

Shrinking the gate

The team that has pioneered the fabrication of III-V MOSFETs with incredibly short gate lengths is Jesús del Alamo’s group at MIT (see Figure 1). These engineers have built planar InAs quantum well MOSFETs with a HfO2 gate dielectric that produce encouraging performance at an operating voltage of just 0.5 V.

Figure 1. Researchers at MIT have fabricated InAs quantum well transistors with a gate length of just 22 nm (left). A high-resolution transmission electron microscopy image reveals the high material quality of this stricture (right).

Corresponding author of the IEDM paper detailing this effort, Jerome Lin, believes that there are four important aspects to the team’s work. “First of all, it’s scalability,” argues Lin. “ For the lateral scaling, we have demonstrated III-V MOSFETs with the smallest gate lengths so far. They deliver fast electron transport and electrostatic integrity down to a 30 nm gate length.” In addition, he says that these devices have shown that vertical scaling is possible. “In order to have the required electrostatic integrity to meet the short-channel-effects goal, we have developed an advanced gate stack.” This has an equivalent oxide thickness (EOT) of less than 1 nm.

The second important aspect to MIT’s work is the self-aligned contact metal process. Lin claims that although this is essential for making a CMOS device, it rarely features in the fabrication of III-V MOSFETs.

According to Lim, the two other breakthroughs described in his the paper are the promising performance of the gate barrier and a fabrication route using a “MOS-like” process. “In the front-end, the process is lift-off free and gold-free.”

The team produced its planar devices on MBE-grown, InP-based epiwafers from Intelliepi. These structures feature a complex, 10 nm-thick channel with a 2 nm InAs core, clad by 3 nm and 5 nm layers of In0.7Ga0.3As. Processing began with the sputtering of molybdenum onto these epiwafers, followed by CVD deposition of SiO2, mesa isolation, and the formation of the gate pattern via electron-beam lithography. Reactive ion etching (RIE) patterns the molybdenum and SiO2 layers, before annealing in nitrogen gas removes RIE damage. A variety of etching techniques then removes some of the epilayers, including a technique that involves plasma oxidation and dilute sulphuric acid. This removes about 0.9 nm of InAlAs or InP per cycle.

With this approach, the team can leave just 1 nm of InP above the channel. Onto this they add 2 nm of the dielectric HfO2 by atomic layer deposition (ALD). Evaporation of molybeum creates the gate contact, which is patterned by RIE and has a gate length defined by the recess opening in SiO2. A pad formation process, which finishes device fabrication, is the only lift-off step. It occurs at the backend of the process.

Transistors operating at 0.5 V and featuring a 30 nm gate length have an electron channel mobility of 4650 cm2V-1s-1 and produce a transconductance of 1420 µS/µm. Sub-threshold swing in these planar devices is just 114 mV/decade, which matches the best finFET III-V devices and is superior to any other planar MOSFET (see Figure 2). Having a low sub-threshold swing is highly desirable, because it enables the device to turn off sharply. Further improvements could be possible, because a similar device with a 300 µm gate produces a sub-threshold swing of just 69 mV/decade.

Figure 2. The sub-threshold swing of MIT’s planar InAs quantum well transistors is comparable to Intel’s Tri-Gate devices.

The team have compared the performance of their gate structure with an Al2O3 gate dielectric. Plotting capacitance as a function of voltage reveals features that are indicative of slow traps close to the mid-gap in the Al2O3-based device – these are not present in the structure containing HfO2. This is encouraging, but Lin insists that there is still more work to do: “We need to reduce trap levels to where not only the best performance, but also the best reliability, can be obtained.”

Intel’s launch of three-dimensional transistors could signal a departure away from the use of the traditional, planar MOSFET architecture to build microprocessor chips. However, Lin argues that the phasing out of planar devices is not a foregone conclusion: “Many papers from industry at the latest IEDM have reported competitive results on planar, ultra-thin-channel silicon-on-insulator FETs. It remains a question which one, or both, will prevail.”

Lin claims that the recent work at MIT demonstrates that planar III-V MOSFETs with a thin channel can offer strong competition to three-dimensional variants: “An important concern for the III-V FinFET is dry-etching damage, which is difficult to anneal in compound semiconductors. Nevertheless, at the 10 nm gate length regime, the FinFET geometry might be the only one that can deliver the required combination of performance and short-channel effects.”

From 3D to 4D

One of the pioneers of three-dimensional III-V MOSFETs is Peide Ye from Purdue University. His group, working in collaboration with researchers at Harvard University, have recently improved the performance of their gate-all-around nanowire MOSFETs, and also taken them in a new direction that they refer to as the fourth dimension − this involves stacking the nanowires horizontallyand vertically (see box “Into the fourth dimension” for details of the architecture of the device and how it is made, and Figure 3 for images of this structure.)

Figure 3. Peide Ye’s team at Purdue University have refined the architecture of their three-dimensional III-V transistors by introducing a two-dimensional array of channels. A top-view of these devices, known as 4D transistors, is provided in the top left image. The top right image shows a cross-sectional SEM image of an InGaAs/InP fin structure fabricated by dry etching, using a hard mask made from Al2O3 and grown byatomic layer deposition. Bottom left: Cross-sectional image shows a 3 by 1 InGaAs nanowire stack. Bottom right: A 3 by 4 nanowire array.

 “The 4D transistor, in principle, can boost drive current and keep the best electrostatic control by the gate-all-around design,” says Ye. He believes that this device delivers the drive current required for the 11 nm node, but its off-state performance needs to be improved.

Advances in the performance of three-dimensional transistors and the introduction of four-dimensional variants build on the work presented by Ye’s team at IEDM 2011. At that meeting in Washington DC they unveiled the first III-V gate-all-around nanowire MOSFETs, which had a relatively high EOT that limited the device’s transconductance, sub-threshold swing and drain-induced barrier lowering (DIBL). The DIBL is an important figure of merit, because it provides an insight into the electrostatic integrity of the device, and how its performance will be impacted by shrinking device dimensions.

They have now addressed these weaknesses by halving the thickness of the Al2O3 gate dielectric from 10 nm to 5 nm, which has improved electrostatic control. In addition, they have boosted the mobility in the channel by switching the composition from In0.53Ga0.47As to In0.65Ga0.35As. Thanks to these changes, typical values for sub-threshold swing in devices with a 50 nm long channel have fallen from 150 mV/decade to just under 100 mV/decade, while DIBL has plummeted from 210 mV/V to just 50 mV/V. Transconductance has also risen, hitting 1.1 mS/µm at a drain-source voltage of 0.5 V.

Results for the four-dimensional transistors, which sport an In0.53As0.47As channel and a 10 nm-thick Al2O3 gate dielectric, are also encouraging. Measurements on a transistor with a 4 by 3 nanowire array with 200 nm long channels produce a transconductance of 0.6 mS/µm at a drain-source voltage of 0.5 V. This value, plus that for the perimeter-normalized drive current, are similar to those produced by the three-dimensional transistors described at IEDM 2011.

Taking these devices and producing them in foundries will be challenging. “The more complicated the structure of the device, the greater the problems of reliability and manufacturability,” admits Ye, who would be delighted to team up with an industrial partner to tackle these issues.

Options for the p-FET

Although germanium is the leading candidate for the hole channel, SiGe and GeSn could yield better results. The latter enables an increase in hole mobility: According to a IEDM 2011 paper presented by a team headed by researchers at Stanford University, switching from a germanium channel to a GeSn alloy with just 3 percent tin boosts hole mobility by 20 percent.

More recently, these engineers from Stanford have developed a complimentary electron channel in collaboration with researchers at imec, KULeuven and GlobalFoundries. According to corresponding author of the paper detailing this work, Suyog Gupta, the attraction of using GeSn for the n-channel − rather than the likes of InGaAs − is that it enables a ubiquitous platform for seemless integration of CMOS logic and silicon-compatible photonics (see Figure 4). “We intend to use germanium tin as a single material platform of high-performance logic and optoelectronics,” explains Gupta, who points out that this alloy is the only group IV material with a direct bandgap, which makes it a very attractive candidate for providing light emission.


Figure 4. A research team led by engineers at the University of Stanford is developing GeSn MOSFETs. Compressive strain can boost the mobility of holes in the p-channel, while tensile strain is needed to enhance electron mobility in the nFETs.

One of the biggest challenges facing the pioneers of germanium and GeSn nMOSFETs is to develop a process that yields high-quality surface passivation. “We have solved this issue for both germanium and germanium tin and achieved a very low high-K/semiconductor interface trap density,” explains Gupta. Fabricating high-quality gates begins with ALD of a 1 nm-thick layer of Al2O3. Oxidation at 400 °C in ozone then creates an interfacial layer of GeSnOx or GeOx, which has a thickness of 2.6 nm, according to cross-sectional transmission electron microscopy images (see Figure 5). These gate stacks have a high-quality interface, according to plots of capacitance as a function of voltage that shows negligible frequency dispersion in depletion and accumulation.

Figure 5. Cross-sectional TEM image of a GeSn MOSFET produced by a collaboration led by researchers at Stanford University. This image reveals that the GeSnOx layer formed by the oxidation process is just 2.6 nm thick.

Gupta explains that one of the benefits of the improved passivation process is enhanced electron mobilities in the nMOSFETs. The room-temperature mobilities in the team’s transistors, which contain between 6 percent and 8.5 percent tin, can get close to 400 cm2V-1s-1. However, electron mobility in these devices is still inferior to those with germanium channels. That’s because the mobility is held back by growth on relaxed germanium buffers, which cause the GeSn to be under biaxial compression, due to its larger lattice constant than germanium. “The compression is one of the reasons why we see an improvement in hole mobility [when switching from germanium to germanium tin],” explains Gupta, who reveals that this strain also reduces the speed that electrons zip through the material. The next step for the team is to form relaxed GeSn. “We believe that this is important, since we expect relaxed germanium tin to show performance enhancements over germanium.”

Improving gate stacks

Very little work has been carried out so far on the unification of post-silicon nFETs and pFETs. This has been accomplished on a germanium platform by a team from the University of Tokyo headed by Shinichi Takagi and Mitsuru Takenaka (see Figure 6), and at the most recent IEDM they reported electron and hole mobilities of 1800 cm2V-1s-1 and 260 cm2V-1s-1, respectively. This represents electron and hole mobility enhancements of 250 percent and 130 percent, respectively, compared with silicon.

Figure 6. Germanium pMOSFTS and InGaAs-on-insulator nMOSFETs have been built side-by-side on germanium substrates by engineers at the University of Tokyo.

Takagi explains that this work is in its infancy: “In this feasibility study the channel length is pretty long. It is 50 or 20 micrometres, though shorter channel devices are also operating.” The operating voltage for these devices is about 2 V.

The paper that they presented at IEDM details a number of recent breakthroughs, including the development of germanium nMOSFETs and pMOSFETs. Built on native substrates, this pair of transistors combined very high mobilities for this material system with very few interface traps and a low EOT. For example, transistors with an EOT of just 0.82 nm and 0.76 nm have produced electron mobilities of 754 cm2V-1s-1 and 690 cm2V-1s-1.

They key to all this success is the novel process for producing the gate, which is a stack of HfO2, Al2O3, GeOx and germanium. ALD is used to deposit a thin film of Al2O3, before oxygen plasma treatment creates a GeOx film under this layer (see Figure 7). GeOx does not get too thick, because the Al2O3 acts as an oxygen barrier, and experiments by the team have shown that just 0.5 nm of GeOx can reduce the density of interface traps. The addition of HfO2 is needed, because Al2O3 has a relatively low permittivity, and limits the EOT to 1 nm. Just using HfO2 on top of GeOx is not an option, as these layers intermix, creating an interface with many traps.


Figure 7. Researchers at the University of Tokyo create GeOx films below Al2O3 layers via oxidation with an ECR oxygen plasma.

Creating a HfO2/Al2O3/GeOx/germanium stack leads to an EOT of just 0.76 nm. “According to the ITRS 2011 [roadmap], EOT at the 11 nm node is 0.76-0.61 nanometres for high-performance applications, 0.86-0.75 nanometres for low operating power applications and 1.1-0.9 nanometres for low standby power applications,” explains Takagi. “So, although 0.76 nanometres might not really be enough for high-performance applications, it is pretty close.”

Takagi and his co-workers have also developed a process for forming germanium-rich MOSFETs on silicon substrates (see box “Building on silicon” for details of this process). This creates a highly strained channel, helping to enhance hole mobility to a value eight times higher that that found in silicon MOSFETs.

When InGaAs, rather than germanium, is used for the electron channel, the indium content is often used to adjust the strain and ultimately the mobility. Takagi and co-workers, however, have been able to decouple the influence of strain from the impact of adjustments in InGaAs composition. “We have changed the strain under a given indium content by using relaxed InGaAs buffers with different indium contents, allowing us to extract the effect of strain on mobility.”


Figure 8. Engineers at IBM have formed InGaAs MOSFETs on silicon using a direct wafer bonding process. Hydrogen implantation into the buffer enables this layer to split under thermal activation.

The team from Tokyo have formed these transistors on silicon. One way to do this is to etch narrow trenches in silicon wafers, and deposit material into these groves to form the channel of the device. Takagi says that in terms of productivity, this approach is the most attractive option, because the only additions to the CMOS process are selective growth processes. “The difficulty [with this approach] is the channel material quality – the lattice mismatch between silicon and both III-Vs and germanium is so large, and so many defects can be introduced into the channels. Aspect ratio trapping can mitigate the density of dislocations, but the material quality has not been proven yet.”

Direct wafer bonding

Takagi and his co-workers have taken a different approach to forming III-V transistors on silicon – direct wafer bonding. This “guarantees” material quality, says Takagi, but he adds that it impairs productivity and probably leads to higher production costs. Another downside of this approach is that it is challenging to realize selective formation of III-Vs and germanium on silicon, and this could constrain chip design.

Lukas Czornomaz from IBM Zurich Laboratory agrees with Takagi that direct wafer-bonding delivers very high material quality, and claims that it is the most mature technology for wafer scale formation of III-V and germanium transistors on silicon. “Direct wafer bonding will be the first to allow a proper technology evaluation at dimensions and densities which are relevant for the semiconductor industry.”

At IEDM 2012 Czornomaz and his co-workers detailed their direct wafer bonding approach (see Figure 8 for an overview). This begins by taking an InP wafer and depositing onto it an InAlAs buffer with a thickness of about 300 nm, a 10 nm In0.53Ga0.47As channel, a 5 nm In0.52Al0.48As back barrier and a 30 nm buried oxide (BOX). A dose of hydrogen is then implanted into the stack, with concentration peaking in the buffer layer (see Figure 9), before the wafer is bonded to a silicon substrate. Thermal splitting separates this structure in two, creating one wafer that is used for making MOSFETs, which has a silicon substrate topped with a BOX, channel, back barrier and some of the InAlAs buffer. This buffer is subsequently removed with a wet chemical etch.

Figure 9. Simulation indicates that a 27 keV implantation of hydrogen leads to a dose that peaks in the centre of the InAlAs buffer (left). Although hydrogen implantation creates defects in the buffer, they are not seen in the active layer channel, which contains the channel and back-barrier (right). 

“The BOX has two functions,” explains Czornomaz. “It first serves to promote the bonding between silicon and III-Vs, which are two very heterogeneous materials. But it is also provides the semiconductor-on-insulator architecture which is needed for device scalability at very small dimensions.”

Initially, the team produced devices with channel lengths down to 250 nm. Values for sub-threshold swing at a source-drain voltage of 0.5 V are typically about 100 mV/decade, and DIBL is around 20 mV/V, which is comparable to Intel’s Tri-Gate devices with similar gate lengths. More recently, the team has reduced gate lengths to 22 nm − results on these devices will be published shortly.

Development of the wafer-bonding process has used 100 mm wafers, because that is the preferred size at the corporation's new Binnig & Rohrer Nanotechnology Center in Switzerland. The team now needs to scale this process to 300 mm, the diameter of silicon wafers used in today’s leading foundries, and this will require a move away from using III-Vs substrates, because they are too small. “We plan to demonstrate that the same approach can be done with III-Vs grown on a large silicon wafer as a donor wafer, which would make it suitable for any wafer size,” explains Czornomaz.

The effort of Czornomaz and his co-workers, plus those at Stanford University, Tokyo University, MIT and Purdue University, show that significant progress is being made towards the introduction of III-Vs and germanium-based transistors on a silicon platform. Further gains are sure to follow in the coming months, and many of them will be reported in the papers given at IDEM 2013. This meeting, which will be held in Washington DC from 6 to 13 December, will provide a snapshot of what’s been accomplished to maintain the march of Moore’s law at the 11 nm node and below – and just as important, what still needs to be done.

 “Into the fourth dimension”

The four-dimensional transistors that are being pioneered by Peide Ye’s team at Purdue University feature a two-dimensional array of InGaAs nanowires. Fabrication begins with the growth of epiwafers on InP substrates. This involves deposition of a 10 nm-thick undoped InAlAs etch stop layer, followed by an undoped 80 nm InP sacrificial layer and a stack of pairs of InP and InGaAs layers: three In0.53Ga0.47As channel layers that are 30 nm thick, sandwiched between 40 nm InP layers.

Uniform doping of the source and drain contacts is realized by a two-step silicon implantation process, using energies of 20 keV and 60 keV and a dose of 1 x 1014 cm-2. Dopant activation resulted from rapid thermal annealing in nitrogen gas for 15 s at 600 °C.

A 10 nm-thick Al2O3 hard m ask, deposited by atomic layer deposition (ALD), paved the way to the formation of fins with a height of 200 nm. These were defined through etching in a mixture of chlorine gas and oxygen, a pairing that is superior to BCl3 for yielding high quality sidewalls. Subsequent etching in a solution based on hydrogen chloride released the nanowire arrays, before the structure was passivated in 10 percent (NH4)S2. After this step, the wafers were immediately loaded into the ALD tool for deposition of Al2O3 at 300 °C, followed by the growth of WN at 385 °C.

The last steps of the fabrication process involved etching to form the base in a mixture of methane and oxygen, and electron beam evaporation of Au/Ge/Ni, followed by lift-off to define source and drain contacts. After forming the source/drain alloy at 350 °C,  Cr/Au test pads were defined.

 “Building on silicon”

Researchers at the University of Tokyo have recently developed a process to form germanium-based pMOSFETs on strained silicon-on-insulator (SOI) substrates. Fabrication of devices begins by taking a SOI substrate, depositing a thin film of silicon on this, and adding a layer of SiGe on top of that (left). This wafer is then oxidized at high temperature, and during this process silicon atoms are preferentially oxidized to form a SiO2 film, while germanium atoms are rejected and transferred to the SiGe film (middle). The buried oxide (BOX) layer prevents germanium atoms from diffusing into the silicon substrate, leading to a steady increase in the germanium content in this layer. Meanwhile, silicon atoms in the SiGe layer diffuse to the interface with SiO2. Once all the atoms of silicon above the BOX are oxidized, a pure film of germanium can be formed (right).