Impact ionization, carrier trapping and leakage paths prevent the channels in today’s HEMTs from providing great transport links between their sources and drains. But improvements should follow, now that these maladies can be exposed with optical and electrical techniques, argue Nicole Killat and Martin Kuball from the University of Bristol.

 

AlGaN/GaN HEMT wafer under electrical and optical testing.

Sales of GaN HEMTs are rising fast, thanks to the performance that they can deliver in RF and power conditioning applications. However, many of these customers buying these devices – which deliver a very impressive set of characteristics – are, for good reason, concerned over the reliability of the transistors. Often this holds back the exploitation of the full power potential of the GaN HEMT.

To address these concerns, researchers must improve this device’s reliability by unmasking and understanding the physical processes provoking device failure. This is happening, with degradation mechanisms in the devices slowly being exposed: Some mirror those found in other types of RF electronics; but others are unique to GaN, and are related to either its material properties, its high electric fields or its high operating temperatures.

Those involved in these efforts must ask themselves one essential question, which will shed light on all the imitations in AlGaN/GaN HEMTs arising from device degradation mechanisms: What happens to the electrons in the device? Or, to put it another way, which obstacles does an electron face on its way from source to drain?

To gain insight into the life of an electron in a HEMT, our team at the University of Bristol, UK, is trying to follow its path through the device and track its behaviour. To do this, we employ a combination of electrical and optical techniques. We know that once an electron leaves the source, it joins its fellows in the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface, before it is accelerated towards the finish line, the drain, by the high electric field.

As the electron heads towards this chequered flag, the chance that it collides with lattice atoms on the way increases. And where collisions occur, it is possible that they spawn a process known as impact ionization. If this does happen, holes formed in the channel layer will create severe device damage once they are accelerated towards the source and gate contact.

This device-degrading event is a very common affliction for GaAs HEMTs. Whether it also occurs in GaN HEMTs, however, is far from clear. It’s a controversial, hotly debated issue, with some arguing that the bandgap of GaN is too large for impact ionization to occur. In GaAs HEMTs, impact ionization is easy to detect – you simply directly measure the generated hole current. But in GaN HEMTs, the higher leakage currents swamp the expected hole current from impact ionization, diminishing the chances of observation of any potential impact ionization electrically.

Optical methods

Hunting for holes with optical techniques offers a more promising route to determining whether impact ionization occurs in GaN HEMTs. Modifying the device structure helps in this endeavour, with the addition of an InGaN back-barrier several nanometres beneath the AlGaN/GaN interface introducing a hole collector and provoking photon emission with very high quantum efficiency. That’s not surprising, given that InGaN is the material of choice for forming wells in the active region of blue LEDs.

Electroluminescence (EL) produced by this modified HEMT features a distinct interband recombination peak at the InGaN bandgap in addition to broad luminescence from hot electron relaxation (see Figure 1). The bandedge luminescence provides evidence of holes in the device, generated at high electric fields and high electron densities. Our measurements show that this strong bandedge luminescence also occurs at cryogenic temperatures, allowing us to rule out hole emission from traps as the hole generation process [1]. Based on these measurements, we can draw the important conclusion that impact ionization is the dominant cause of hole generation and does occur in GaN HEMTs.



Figure 1. Electroluminescence spectrum produced by an AlGaN/GaN HEMT formed on SiC during on-state operation. This device features an InGaN back-barrier, which enhances the optical output.

More can be learnt about the behaviour of electrons as they pass through the transistor from the low energy tail in the EL spectrum. This reveals that, in the channel of the device, electrons undergo relaxation processes that don’t involve recombination with holes. The spectral distribution offers an insight into the temperature of the electron and its fellows, showing that they can easily reach several thousand degrees – ten or more times higher than that of the lattice. Impact ionisation and hot electron relaxation can be accompanied by other mechanisms, such as electron-phonon and interface scattering [2].

Electronic traps

Electrons passing along the channel can face other obstacles. These include electronic traps, which can have a direct or indirect impact on its life and the related current density. One type of electronic trap is associated with defect states, which capture and release electrons within a characteristic time, thereby modifying the electric field distribution near the device channel. Identifying the location of traps in degraded HEMTs is very challenging. The most common approach is to turn to simulation to estimate the location of the traps, based on a fit to electrical device characteristics. This is a valuable, but rather indirect approach.

In another class of device, a large-area capacitor, gate-capacitance-based measurements, such as conductance techniques, are widely used to evaluate trap characteristics. However, this approach cannot be transferred to short-channel devices, because inaccuracies are far larger, due to the weak capacitance signal offered by the small gate area. In contrast, dynamic transconductance does not require capacitance measurements to extract the trap conductance [3]. In this case, both the interface and the bulk traps are detected and distinguished by analysing bias dependence of the extracted conductance (see Figure 2 for an example of bulk trap conductance).



Figure 2. Bulk trap conductance, Gp/ω, can be determined from transconductance measurements as a function of frequency for different base-plate temperatures. The inability of channel electrons to follow the pulsed gate signal leads the conductance to peak at a certain frequency related to the trap-specific time constant. This technique enables the detection of traps at a density of 1011 cm-2eV-1 and below, in particular those located at or near the AlGaN/GaN interface in GaN HEMTs. In this case, the traps were identified as bulk traps with a temperature-dependent time constant ranging from 10-2 to 10-4 s and an activation energy of 0.7 eV, located in the GaN buffer layer. This device has a 0.25 µm gate length, and the data was fitted to a model (solid lines) representing a continuum of trap energy levels.

In addition to bulk and AlGaN/GaN interface traps, surface and subsurface traps can impact the path of the electron as it passes along the channel. If the traps are near the gate, they affect the electric field in the channel that governs the electron transport. UV-assisted transient trapping is capable of locating and identifying electronic traps in GaN HEMTs. This technique involves applying a trap-filling pulse at a high negative gate-source voltage and then recording the de-trapping transient in on-state operation. Exposing the transistor to UV-light exposure prior to the filling pulse can modify the electronic trap population.

We have determined the current transient trapping characteristics for GaN HEMTs illuminated with UV light of different photon energies (see Figure 3). These measurements reveal three trap states with different time constants: Only the slow trap is strongly affected by light exposure. When illuminated with photon energies between the bandgaps of AlGaN and GaN, these devices show a large trapping amplitude, indicating that the traps are located in the AlGaN barrier close to the gate (see the inset of Figure 3).



Figure 3. Transient current-trapping characteristics of an AlGaN/GaN/SiC HEMT. A trap-filling pulse was applied at VDS = 0 V, VGS = -10 V, with subsequent transient measurements at VDS = 0.5 V, VGS = 1 V. The current transients are labelled with the photon energy of the UV light exposed to the device prior to measurement.

These traps are probably caused by oxygen reactions at the device surface [4], which can reduce the electric field in the electron channel. The consequences of this are not limited to reduced electron acceleration in the channel, and include partial depletion of the 2DEG and a subsequent decrease in drain current.

When surface trap density increases during device operation and electrical stressing, leakage pathways are formed through the AlGaN barrier to the device channel. Leakage current then rises during device stress, correlating with the appearance of EL spots during off-state operation [5]. We have noted that there are localised EL spots along the drain edge of the gate – where the maximum electric field is located – that multiply in number during device stress (see Figure 4). The appearance of each new spot coincides with a step increase in the gate leakage current (Figure 4(c)), illustrating that this progressive appearance of EL hot spots tracks a gradual ‘breakthrough’ of the AlGaN layer in the device.

After removing the metallic contact and passivation layer, we scrutinized the semiconductor surface with an atomic force microscope (see Figure 4(b)). Imaging revealed a one-to-one correspondence between EL spots and the generation of large pits on the surface, which are associated with the breakthrough of the AlGaN layer. These observations reveal the direct link between EL spots, surface pitting and the generation of a gate current leakage path during off-state stress (see the inset of Figure 4(c)).



Figure 4. Hotspots in AlGaN/GaN HEMTs. (a) EL image of a representative device after off-state stress overlaid with a white light image (b) AFM images of the area marked in (a) after removal of contacts and passivation layer (c) gate leakage current during off-state stress. Arrows indicate the gate currents steps that coincide with the appearance of EL spots.

To ensure a safe journey of the electron, gate engineering is often used to trim the maximum electric field near the gate edge. This limits trap generation and the formation of EL hot spots. Common ways to do this are to use field-plates and slanted gates that spread out the peak electric field, reducing its peak value. Surface trapping subsequently falls, as can be seen in gate lag measurements (see Figure 5). It is also possible to move the peak electric field into the device’s barrier layer by including a gate recess [6]. Transistor architectures sporting slant and slant-recessed gates present a low gate lag even after electrical stress, so they are favoured for the fabrication of GaN HEMTs with high device reliability.



Figure 5. Gate lag for two different gate shapes: I-shaped (black) and slant recessed (blue). Solid and dashed lines show the gate lag as a function of source-drain voltage before and after an off-state stress.

Our efforts show that electrical and optical methodologies can expose many different degradation mechanisms, including impact ionization, charge carrier trapping and leakage path generation. These imperfections can degrade device performance and reliability, so understandings which ones are prevalent in a particular transistor architecture is a major aid to designers, who can reduce the obstacles in the path of a channel electron and give it an easier passage to the drain - its final destination.





Typical experimental setup used for combined electrical and optical 

device testing, including Raman thermography, photoluminescence and 

electroluminescence analysis as well as device stressing and transient 

trapping analysis.

We acknowledge financial support from Office of Naval Research under the DRIFT programme (monitored by Paul Maki), the European Defense Agency (EDA) under the MANGA programme and the EPSRC. We thank T. Palacios (MIT) U. K. Mishra (UCSB), and QinetiQ for providing devices for the studies. 

References

[1] N. Killat et al. Electronics Letters 47, 405 (2011)

[2] J. W. Pomeroy et al. physica status solidi (b) 245, 5, pp. 910-912 (2008)

[3] M. Silvestri et al. IEEE Electron Device Lett. 33, 11 (2012)

[4] M. Ťapajna et al. Reliability Physics Symposium (IRPS), 2010 IEEE International 152 (2010)

[5] M. Montes Bajo et al. Appl. Phys. Letters 101 033508 (2012)

[6] J. Möreke et al. physica status solidi (a) (2012)