Cutting cell costs will ensure that concentrating photovoltaic systems become more competitive. One way to do this is to turn to silicon substrates incorporating germanium-based layers, which bridge lattice constants and allow the formation of a 1 eV junction for boosting efficiency, say Andrew Clark, David Williams and Radek Roucka from Translucent.

Even in countries that are not renowned for good weather, you don’t have to look too hard to find solar panels on the roofs of houses and businesses and lined up across fields. Their widespread deployment in recent years has been driven by a combination of feed-in tariffs and ever-more-competitive purchase prices, which have plummeted over the last two decades.

Falling costs over a similar time frame have also taken place in the concentrated photovoltaics (CPV) market. Here, the triple-junction cells that lie at the heart of these systems and convert light focused by mirrors or lenses into electricity at efficiencies of around 40 percent were once only used for powering satellites; but now they are also on the ground, generating power for utilities.

One obvious step for making CPV systems more competitive with other forms of energy generation is to combine two technologies – that is, to take a low-cost silicon wafer and use it as the basis for forming many highly-efficient, multi-junction devices featuring various compound semiconductor layers. At Translucent of Palo Alto, CA, that is exactly what we are trying to do, with a technology platform that we refer to as our ‘on-silicon solution’. Just like our other ‘on-silicon’ technology – GaN-on-silicon via rare earth oxide buffers [1] – the cost drivers behind our approach are large-form-factor wafers, which utilise existing silicon fabrication equipment and infrastructure. 

However, for CPV, silicon has some additional benefits: It has a higher thermal conductivity than germanium, simplifying cell cooling; and it is also mechanically stronger for any given thickness, so it can be scaled easily without a thickness penalty.

Our core technology is to use group IV binary alloys, such as GeSn, to defect engineer the interface between silicon and the germanium epitaxy. We also insert silicon into some of the films in our epitaxial stack, because this allows us to create ternary alloys with a bandgap around 1eV, which hold the key to forming ultra-high efficiency sub cells.

Assessing the options

We are by no means the first team to try to unite III-V materials with silicon wafers for photovoltaic applications. Others have been trying to do this for the past few decades, with attempts focusing on germanium-based buffer layers. These have been added with various schemes, including: the addition of thick, graded SiGe buffer layers with incorporated chemical mechanical polishing; low-energy, plasma-enhanced CVD growth; and wafer bonding. All these approaches suffer, to some extent, from defects propagating into device layers. These imperfections originate from the lattice mismatch between germanium and silicon. Efforts have focused on making a buffer layer from germanium, because this material has a dual function in triple-junction cells: It is the substrate and it forms the low-energy cell in triple-junction devices featuring mid-energy and high-energy cells built from InGaAs and InGaP, respectively. This three-cell combination can yield a device with an efficiency in the 37 percent to 43 percent range.

Other schemes promise to reach even higher efficiencies. One notable example is the proposition from the NREL to incorporate an additional 1eV junction based on an alloy from the GaNAs family, specifically Ga1-xInxNyAs1-y [5]. This quarternary can be lattice matched to GaAs or germanium by selecting the value of y so that it is around 0.35x. To date, the most successful use of this material has been achieved by the Californian company Solar Junction, which raised the bar for multi-junction cell efficiency to 44 percent [6]. It is also possible to reach the 1eV bandgap with SiGeSn alloys, which is an approach that has been pioneered by researchers at Arizona State University [7].

We are playing our part in propelling multi-junction cells to higher efficiencies by developing a high quality group IV template of germanium that is grown directly onto a silicon wafer, and then adding a lattice-matched SiGeSn structure that will allow the formation of a 1eV junction. Subsequent addition of III-V materials allows the formation of upper junctions to create a device architecture with the potential to deliver very high efficiencies.

This approach offers an ‘on-silicon’ technology for CPV that addresses mechanical issues –  such as defect propagation, thermal mismatch, and cracking –  and offers a roadmap to an ultra-high efficiency CPV sub-cell.

Building the platform

Our first objective has been to develop a virtual germanium substrate on silicon that offers the same characteristics as bulk germanium. To meet this criterion, our engineered substrate must: function as the bottom germanium junction; and provided a template for MOCVD that allows the growth of lattice-matched III-V layers for forming higher-energy cells. According to analysis of the solar spectrum relative to the cell design, the germanium layer must be at least 5 µm-thick in order to absorb 85 percent of the solar radiation transmitted by the top III-V junctions in a multi-junction cell. Such a device will combine ultra-high efficiency with low manufacturing costs, because it can be initially formed on 150 mm silicon wafers, before being quickly transferred to a 200 mm platform.

To make this happen we have had to circumvent complications associated with direct growth of germanium on silicon – normally this leads to the growth of rough, highly defective layers, due to a significant difference in lattice constant between the two materials (it is 5.41 Å for silicon and 5.66 Å for germanium). We avoid this trap with a novel deposition approach, which was originally developed at Arizona State University and has been modified for pilot production at our Palo Alto plant. It is based on a low-temperature, ultra-high-vacuum (UHV) CVD process.

At our headquarters, we use this to deposit germanium on silicon in a custom-designed horizontal furnace that is capable of simultaneous growth on multiple 150 mm wafers. Germanium is synthesized at low growth temperatures on silicon (100) wafers using digermane (Ge2H6) and deuterated tin (SnD4) precursors. For the growth of thick, virtual germanium-on-silicon templates, a small amount of tin precursor is injected into the chamber during the growth. Its atomic concentration in the final layer is less than 0.5 percent, so it does not influence the structural, optical, or electrical properties of the germanium template.

However, at these levels tin is able to play a valuable role, modifying the germanium-silicon interface by promoting the formation of misfit dislocations. They are tied to this interface and do not propagate into the germanium layer. Attributes of our low temperature UHV-CVD technology include control of the tin content in the film and the opportunity to realise compositions well in excess of 0.5 percent. In the 1-2 percent range (as shown in figure 1) Ge1-xSnx becomes a true binary alloy – compared to germanium, it has a larger lattice parameter and greater optical absorption.

Figure 1. Effect of tin incorporation into group IV alloys

A larger lattice parameter is a tremendous asset, bringing a new degree of freedom to the design of the multi-junction sub cell devices. In the majority of today’s production-qualified III-V multi-junction devices, the fixed lattice parameter of the germanium wafer constrains III-V layer compositions and consequently the bandgaps of each of these layers. In contrast, the more flexible GeSn lattice allows the entire III-V material stack to be engineered, and this ultimately promises to increase photovoltaic energy yield and efficiency (see Figure 2).

Figure 2. Incorporation of tin into germanium breaks the germanium constraint and enables optimized design of III-V cells

The full potential resulting from the addition of group IV alloys to CPV material engineering only comes when silicon is added to GeSn. This is possible by injecting the precursor trisilane (Si3H8) into the growth chamber. Switching from a binary to a ternary, in this case from GeSn to SiGeSn, allows the lattice spacing to be fixed while the bandgap can vary (see Figure 3). This is the path that we are promoting to add the desired 1eV sub cell to the multi-junction cell (see Figure 4).

Figure 3. A simulation and three-dimensional plot showing ternary composition verses bandgap for SiGeSn

Figure 4. Efficiency evolution by the application of both lattice and bandgap engineering can be enabled via incorporation of group IV SiGeSn alloys as shown by this modelling graph of efficiency with four different types of sub cell design (courtesy of Yong Hang Zhang, ASU)

Proving the concept

We select a particular type of silicon substrate for our work, because we must ensure that the germanium that is formed on it has the same crystalline orientation as that currently used in bulk substrates; that is, for photovoltaic templates we employ silicon with a 6° mis-cut toward the direction.

The germanium grown on this has incredibly high purity. According to compositional analysis providing by Rutherford Back Scattering and X-ray diffraction measurements, the germanium layer, which can readily reach 5 µm or more, has a tin content of just 0.05-0.3 percent. This layer is optically flat and smooth, with atomic force microscopy images revealing a root-mean-square surface roughness as low as 0.8 nm on 5 µm x 5 µm scan. Morphology of the virtual germanium wafer typically resembles the stepped surface produced on vicinal substrates. 

Crystalline quality of the germanium is excellent, with double-crystal X-ray diffraction measurements giving a full-width half maximum for the germanium (004) reflection as low as 0.05 degrees (180 arcsec), while defect measurements performed by chemical etching methods indicate that defect densities can be as low as the order of 1 × 106 cm-2. Capacitance-voltage measurements indicate that the Ge(Sn) material is p-type, with a carrier concentration of 1 × 1017 cm-3.

To take advantage of all these attractive qualities in a commercial manufacturing environment, the template must be compatible with existing upstream processes. For MOCVD, a key requirement is that the surface miscut on the silicon substrate is carried through to the germanium layer, where it is needed to prevent the formation of anti-phase domain boundaries. The good news is that reciprocal space mapping of epitaxial germanium-on-silicon shows the magnitude of the surface miscut (5-6°) is preserved (see Figure 5).
Figure 5. X-ray reciprocal space mapping confirms that surface miscut of the epitaxial GeSn is the within one degree of the underlying silicon substrate [ 6° off to ]

An important tool specification in the silicon industry is wafer bow, which often has to be below 50 µm. If it exceeds that, it leads to problems with the automatic wafer handlers in the silicon lines. Our engineered wafers are well within this specification, with three-dimensional scanning techniques revealing that the vertical distance between the edge and centre of the wafer is less than 30 µm for a 5 µm-thick germanium template (see Figure 6).

Figure 6. Growth of 5 µm of germanium ‘on-silicon’ does not exceed a wafer bow of 30 µm, allowing this meet the specification for silicon lines

These engineered substrates are now being evaluated by commercial partners, who have proceeded with trial growth of III-V materials and device structures by MOCVD. Pilot runs confirm that our virtual germanium/silicon substrates are suitable for subsequent MOCVD growth, and just a minor modification is required to the growth recipe for the nucleation layer. Initial tests included the growth of thick, lattice-matched InGaAs layers with 1–2 percent indium concentration (see Figure 7).  Secondary ion mass spectrometry analysis confirms the stability of the virtual germanium/silicon substrate, and the absence of diffusion into III-V material. Simple, trial solar cell devices have been produced with this platform, and they exhibit acceptable fill factors and open-circuit voltages (see figure 8).

Figure 7. Transmission electron microscopy image of the 2 µm-thick InGaAs layer grown by MOCVD on Translucent virtual-germanium template
 
Figure 8. Current-voltage characteristics of a single junction solar cell grown on both germanium templates and bulk germanium

When these vertically integrated devices are formed that involve direct growth on silicon, the germanium layer acts as one of the junctions, while the silicon wafer is used as the bottom contact layer. In this type of device, p-type doping must be added during the epitaxial process. This is possible: Initial trial runs show no adverse interactions between boron, germanium and tin, and template wafers have been formed with doping levels of 5 x 1017 cm-3 to 3 x 1018 cm-3, which is an ideal range for base layers in the structure.

Goals for the future

Our challenging journey has focused on designing a 1eV layer into a sub cell structure that is silicon-based, and includes group IV materials and III-Vs. Significant strides in this direction have already been made – such as forming templates based on thick Ge(Sn) layers lattice-matched to silicon, and the growth of III-Vs on top of templates to form photovoltaic structures – but there is much more to do. This includes incorporating doped junctions, multi-junction structures, and SiGeSn films for the 1eV layer to access ultra-high efficiency devices.

While much of the focus so far has been on interface engineering, lattice engineering, and bandgap engineering, this must now be allied to continual optimization of crystal growth and device structural design, as this multi-pronged effort will hold the key to improving results very quickly in the coming months.

References
1. M. Lebby et. al. Compound Semiconductor July 2012, p 37
2. S. Ringel et. al. MRS Proceedings 836 “III-V multijunction materials and solar cells on engineered SiGe/Si substrates (2004)
3. R. Hinige et. al. Semiconductor Science and Technology 21 775 (2006)
4. S. Thomas et. al. IEEE Electron Device Letters 26  428 (2005)
5. NREL reference (http://sunlab.site.uottawa.ca/pdf/whitepapers/HiEfficMjSc-CurrStatus&FuturePotential.pdf
6. PRN Newswire, 15th October 2012 “Solar Junction Breaks it’s own world record”
7. R. Soref et. al. Mat.Res.Soc.Symp. Bol 958 (2007) 0958-L01-08 “Advances in SiGeSn/Ge Technology”