Belgium and Japan-based researchers unveil an improved process to integrate germanium-tin layers and MOSFETs on silicon substrates. Compound Semiconductor reports

Researchers from the Katholiek University of Leuven, the IMEC research institute at Leuven and Japan's National Institute of Advanced Industrial Science and Technology (AIST)  have unveiled a solid phase epitaxy process to integrate germanium-tin MOSFET devices on silicon.

Having fabricated depletion-mode junctionless GeSn p-MOSFET on silicon prototypes, the team believes the process paves the way to making faster electronics and optoelectronics devices, such as GeSn photodetectors on silicon, for optical communications applications.

To improve the performance of next-generation CMOS transistors, researchers worldwide are integrating novel materials to silicon, to increase carrier mobility and the switching speeds of these devices. Germanium is already widely added to silicon to do just this, but for sometime now, researchers have been attempting to add tin to germanium, to boost carrier mobility further.

"By adding tin to germanium, we improve both the electron and hole mobility and lower the difference between the direct and indirect transition, so the material gets closer to being a direct bandgap material," explains Ruben Lieten, research associate at imec.

However, while other researchers have strived to achieve this, the limited solubility of tin in germanium under equilibrium conditions and the introduction of compressive strain when depositing on germanium substrates has hampered progress. With this in mind, Lieten and colleagues set out to develop a process that would not only overcome solubility issues but also allow them to integrate GeSn channel transistors onto silicon substrates, ready for CMOS processes.

TEM image of NiGeSn metal S/D MOSFET. [imec]

Novel fabrication

To fabricate their MOSFETs, the researchers wanted to deposit ultrathin and biaxially strained single crystalline GeSn layers directly onto silicon substrates. As Lieten highlights, ultrathin GeSn layers on silicon have a good band structure for depletion-mode pMOSFETs. What's more, the biaxial tensile strain helps to reduce the difference between the direct and indirect transition, bringing the  GeSn material closer to being a direct bandgap semiconductor.

Germanium and tin were first evaporated from separate MBE effusion cells in an ultrahigh vacuum chamber, and then deposited at low temperature and in nitrogen, via MBE, onto cleaned silicon substrates to form a ~40nm amorphous GeSn layer. The substrate was then removed from the MBE chamber and annealed, in nitrogen, to transform the amorphous GeSn layer to a single crystalline tensile-strained layer via solid phase epitaxy. The biaxial tensile straining is attributed to the thermal expansion coefficient mismatch between GeSn and silicon.

According to Lieten, exposing the silicon substrate surface to an inert gas during MBE deposition is crucial to achieving amorphous GeSn layers with a high Sn content. "[Nitrogen] limits adatom diffusion [of germanium and tin] on the silicon surface, helping to prevent crystalline seeds forming in the deposited layer," he says.

As he adds: "It is important to start from an amorphous layer without the presence of crystalline grains that would induce the formation of a polycrystalline film, as the silicon substrate can then impose its structure onto the amorphous layer, during annealing."

The novel process took place at non-equilibrium conditions, which says Lieten, allowed the researchers to incorporate much more tin - analysis put the concentration at 4.5% - than would have been possible with liquid melt processes that typically yield 0.5 to 2.0% tin in germanium.

What's more the tin was evenly distributed throughout the GeSn layer, with no sign of tin segregation at the surface, interface or within the layer.

"When you use non-thermodynamic conditions, you can 'freeze' in more tin," explains Lieten. "CVD and MBE growth of GeSn on silicon takes place at such non-equilibrium conditions that you can get more tin into the germanium matrix. Indeed other groups have reported up to 20% tin in GeSn alloys under these conditions."

And according to Lieten, their the new method takes place under more extreme non-equilbrium conditions, so even higher concentrations of tin can be incorporated.

With the layers deposited, the researchers went on to fabricate GeSn junctionless, pMOSFETs with a TaN/Al2O3 gate stack and NiGeSn metal source drain, with great results. Thanks to the structural quality of the GeSn channel layer, the hole mobility in the transistors increased by more than 100%, relative to p-type bulk silicon devices, with the device demonstrating an on/off ratio of 84.

Being junctionless also removes the need for source and drain formation, which the researchers say makes carrier transport less sensitive to the channel interface.

But despite success, research continues. According to Lieten, his germanium source material contained low concentrations of gallium. "This led to a high-p-type concentration in the channel so we need to remove this dopant to get better gate control and higher mobility," he says.

What's more, during this round of fabrication, the researchers used reactive ion etching to reduce the channel thickness from ~40 nm to ~10 nm and better control the off-current. "But this leads to severe roughening of the layer which lowers the carrier mobility," explains Lieten. "We will now omit this process."

And Lieten also wants to reduce twinning defects in the layers. ""We need to look deeper at the types of defects that are present," he says. "With the latest samples we had twinning and it was difficult to assess the type and density of threading dislocations as these defects were shadowed by the presence of twins."

Still, the material system has demonstrated very promising properties and the team will be looking to improve the structural and electrical properties of the material further. Crucially, Lieten has also used plasma-enhanced CVD to fabricate pure germanium layers through solid phase epitaxy, a process more tailored to industry scale fabrication.

Meanwhile, other researchers are using the combination of germanium and tin to develop mid-infrared LEDs and laser diodes.

"Because we have a direct bandgap, we can emit and absorb light much more efficiently," he says. "Some researchers are working on LEDs and even laser diodes. You can make the emission source and detector from GeSn and then integrate these together with GeSn CMOS transistors on a silicon substrate."