To maintain the improvements in efficiency that traditionally result from shrinking transistor dimensions, foundries will soon have to replace silicon channels with those based on higher mobility semiconductors. This move, a monumental upheaval for the silicon industry, could be easiest to implement by turning to engineered wafers with separate layers for the p-type and n-type transistors, argues Lukas Czornomaz from the Advanced Functional Materials Group at IBM Zurich.

Four decadesof scaling CMOS technology has revolutionized our society. By making transistors ever smaller, faster, cooler, and cheaper, and being able to pack billions of them on the same chip, engineers have enabled the smartphone to become a commodity. This sleek, portable device has fundamentally changed the way we live: Now, wherever we are, we can be participating members of social networks and surfers of the web.

Performance of the smartphone will continue to increase, but it will not be easy to realise further gains in the computational capability of the chips that lie at the heart of these devices. That’s because the microelectronic industry is facing some really serious challenges in shrinking dimensions beyond the 14 nm node.

Even getting as far as we have today has not been easy. For the last decade, pure geometrical scaling has failed to deliver the expected benefits in terms of performance and power consumption, and industry has gradually moved to innovation-driven scaling, bringing to market chips based on the likes of strained silicon-on-insulator, high-k/metal gate technology and tri-gate devices. Now researchers everywhere are foreseeing that in the coming years, silicon – regardless of its form - will probably fail to meet the ultra-low power consumption targets imposed by the exploding demand of ‘Mobile-Everywhere’ applications.

The main lever for power scaling is the operating voltage of the chips. The target is to trim this from 0.8-0.9 V, which is where it stands today, down to 0.5 V. This cut in operating voltage must go hand-in-hand with a maintaining of the drive-current for the transistors, in order to ensure no reduction in performance. But realising this will not be easy. It will require the charge carriers in the transistor’s channel – either electrons or holes, depending on the particular transistor − to travel far faster from the source to the drain. Today, increases in the charge carrier velocity in silicon often result from the application of very high levels of strain in the material, but the opportunities for further gains are now minimal, especially for n-type transistors. 

What is possible is that the next revolution in the semiconductor industry will come from the introduction of compound semiconductors as channel materials. Electron and hole mobilities in silicon are just 1400 cm2 V-1 s-1 and 450 cm2 V-1 s-1, respectively, and far higher values are promised by switching to carefully selected III-V and IV-IV compounds. For example, the electron mobility in InGaAs is in excess of 10,000 cm2 V-1 s-1, while hole mobility in SiGe can hit 1900 cm2 V-1 s-1. Using these materials to form thep-type andn-type transistors for CMOS chips would allow the indium and germanium content in the channels to become a new scaling parameter, gradually increasing the carrier velocity for each new technology node and thus improving performance while lowering power consumption.

Researchers will have to answer many questions before it is possible to build hybrid dual-channel CMOS circuits featuring very-large-scale integration (VLSI). They include: How do you get high-mobility channels on a silicon substrate with a good crystalline quality? How do you build nano-scaled devices based on III-Vs and SiGe that are compatible with VLSI? And how do you co-process both types of devices, given the fundamentally different thermal budgets and chemistries that they require?

A team at the IBM Zurich Research Laboratory in Switzerland has been focusing on finding answers to these questions for the last eight years. Efforts have now paid dividends: They have developed novel engineered substrates and process technologies for high-volume manufacturing in silicon foundries of VLSI circuits with compound semiconductor materials.

Silicon foundations

Although the microelectronic industry will have to undergo some big changes in the coming years, this will not include a change in substrate. So, to enable III-V and IV-IV compounds to be integrated in CMOS production, these materials will have to be introduced on a silicon substrate.

This is not easy, because integration of different, high-quality crystalline materials demands a matching of crystalline arrangement and lattice constant. While InGaAs, germanium and silicon have a similar crystalline arrangement, their lattice constants are significantly different: Compared to silicon, the average atomic spacing is about 4 percent larger for germanium and 8 percent larger for InGaAs. It is possible to manage the lattice mismatch for SiGe and germanium with some engineering tricks, but this is not possible with InGaAs, because the mismatch between this alloy and silicon is far too high. If attempts are made to grow InGaAs directly on silicon, strain in the ternary is so high that this material relaxes by forming an excessively large number of crystalline defects, which would significantly degrade device performance.

Today, to overcome this defect-related weakness, industrial researchers are pursuing two approaches. One of the options is known as aspect ratio trapping, while the other – pioneered at IBM – is called direct wafer bonding (see Figure 1 for an overview).



Figure 1. Comparison of the two main routes to integrate III-V on Si substrates: Aspect ratio trapping (on the left) and direct wafer bonding (on the right)

Aspect ratio trapping exploits the defined angles of the crystalline defects. The starting point is to take a silicon substrate and etch out a narrow trench – that is, one with a high aspect ratio, or in other words a groove with a height that is several times greater than its width. When III-Vs are grown directly in this trench, defects form at the interface and propagate along defined angles, before terminating on the trench walls. Thanks to this defect-elimination process, a low defect InGaAs crystal is created at the top of the trench. However, while this argument is applicable across the trench, where there is a high aspect ratio, it fails to hold true along the trench, where defects can propagate to the top channel material. This means that the channel material sitting on top of the trench is located on top of a defective semiconductor, which creates potential leakage paths from source to drain.

Aspect ratio trapping also restricts the availability of InGaAs. As this ternary is only present above the trenches, circuit designers are restricted in their positioning and sizing of the transistors. However, this issue disappears if the trenches can be tied together at a very small pitch, as required for the silicon fins of today.

Despite all these drawbacks associated with aspect ratio trapping, it still attracts a lot of attention, because it is directly compatible with silicon foundries that are now running 300 mm lines and could upgrade to 450 mm. However, foundries may find it much easier to pursue the technology that IBM is developing: direct wafer bonding.

With this approach, thin layers of III-Vs can be transferred onto silicon in the same manner already employed by industry to build silicon-on-insulator (SOI) substrates. Engineers simply grow the InGaAs layer on a donor substrate, before bonding it via an oxide to a target silicon substrate. The thin III-V layer is then released from the donor wafer to yield a III-V-on-insulator structure on silicon. This approach allows the donor wafer to be recycled, thereby maintaining the cost-efficiency of this process.

There are many attractive attributes associated with having a very thin III-V channel on an insulator. This

combination is an ideal structure for maintaining good electrostatic control of the gate over the channel at short gate lengths, and it efficiently cuts leakage currents from source to drain. What’s more, this combination enables the use of the back-biasing technique, which permits dynamic adjustments of the transistor’s operation, so that it can be tuned to be faster or more power-efficient. All these merits reveal why III-V-on-insulator could be the preferred option for low power applications, such as mobile electronics.

The Zurich researchers have used wafer-bonding to create a hybrid, dual-channel substrate that uses a thin insulator to separate a 6 nm-thick InGaAs film from an 8 nm-thick SiGe layer on a silicon substrate (see Figure 2). This engineered platform has enabled both channel materials to be integrated on the same substrate for the first time, while matching the thickness requirements of the 14 nm technology node. This breakthrough should pave the way towards the production of dual-channel CMOS circuits, where n-type transistors could be built on InGaAs and p-type transistors on SiGe.



Figure 2. Photograph and associated cross-sectional illustration of a high-mobility dual-channel substrate which comprises a 6 nm thick InGaAs layer on a 8 nm thick SiGe layer on a silicon handling substrate

III-V challenges

As readers of this magazine all know, III-V materials have been used for many years for the manufacture of myriad RF/analog chips, LEDs, lasers, solar cells and high-power devices. However, although a lot of know-how has been developed and accumulated over several decades, none of these applications require the fitting of billions of devices onto an area the size of a fingernail – a requirement imposed by CMOS chips. This additional constraint forces engineers and scientists to revolutionize the way III-V devices are fabricated, because gate lengths must be shorter than 20 nm, and, more importantly, contacts have to fit in less than 50 nm.

These pre-requisites cannot be met by turning to different lithography levels to define the different elements of the devices, because transistors are way too small. Instead, a so-called self-aligned process has to be developed that enables the construction of all the different building blocks of the device with a single lithography step: the gate definition. By taking this approach, device dimensions and device pitches can be aggressively scaled to meet the requirements of VLSI integration.

In 2012, the Zurich team showed that it is possible to fabricate self-aligned InGaAs transistors. These VLSI-compatible devices feature a gate-first high-k/metal-gate process with raised source-drain regions, which are just like those employed in industry for the manufacture of the most advanced silicon CMOS technology nodes.

The first ‘bulk’ transistors were fabricated on InP wafers (see Figure 3a), with successful operation down to gate lengths as small as 60 nm. The team then went one better, transferring the fabrication flow to III-V-on-insulator substrates on silicon, which had an InGaAs channel layer just 10 nm-thick (see Figure 3b).



Figure 3. (a) Cross-sectional TEM view of a “bulk” self-aligned InGaAs transistor on InP featuring high-k/metal-gate technology and raised source-drain. (b) Cross-sectional TEM view of an InGaAs transistor fabricated with the same process flow but transferred on a III-V-on-insulator on Si substrate. (c) Comparison of DIBL versus gate length for both types of transistors showing up to a factor of five reduction for devices on insulator

Within the SOI industry, it is well known that this class of engineered substrate offers a large performance boost, thanks to the confinement of the carriers in a very thin channel and better electrostatic integrity. Superior performance translates to a reduction in the drain-induced barrier lowering (DIBL) of the transistors by up to a factor of five (see Figure 3c). DIBL is a key figure-of-merit for the electrostatic performance.

Further accomplishments by IBM Zurich include the construction of InGaAs transistors with a 24 nm gate and a gate-to-gate spacing of just 300 nm (see Figure 4). To date, they represent the smallest, most compact VLSI-compatible InGaAs transistors reported on silicon.



Figure 4 (above). Cross-sectional TEM view of densely packed InGaAs devices on silicon substrates with gate lengths of only 24 nm

Dual channel developments

In addition to building standalone devices, the advanced dual-channel substrate technology can be used as a base for building small CMOS circuits. One of the benefits of this approach is that both channel materials are stacked on top of each other, so are present everywhere on the wafer. After defining some islands where transistors should be, the InGaAs channel can be removed to expose the SiGe channel where p-type devices are to be built (see Figure 5a).



Figure 5. (a) Schematic process flow for the fabrication on hybrid InGaAs/SiGe CMOS circuits based on high-mobility dual-channel substrates. (b) Top-view SEM image on a dense CMOS inverter chain fabricated with 90nm design rules. (c) Hybrid CMOS inverter output characteristic showing a working circuit

Although having both InGaAs and SiGe channels on the same wafer is an enviable starting point, this comes at the penalty of more challenging material processing. InGaAs and SiGe exhibit fundamentally different chemical natures, so processes that work fine with one material can cause etching of the other. To address this, the researchers modified the fabrication flow for building InGaAs transistors on insulator, introducing new chemical cleans, passivation and etch-stop layers.

Thanks to all these developments, the team has have been able to demonstrate the first construction of dense arrays of CMOS inverters built with 90 nm design rules on silicon substrates that feature high-mobility channel materials (see Figure 5b). Inverters are the simplest logic block, and an important step towards the building of more complex CMOS circuits. Thus, by showing an InGaAs/SiGe inverter operating down to 0.2 V (see Figure 5c), the concept of using high mobility materials for CMOS has been validated. What’s more, the door has been opened to further developments that could ultimately enable an up-scaling of the technology for high-volume manufacturing.

Clearly, the next steps are to build more complex CMOS circuits such as ring-oscillators and SRAM cells (a very common memory cell featuring six transistors). Armed with these circuits, the team will be able to assess the speed, performance and maturity of this advanced CMOS technology. However, the key test for this hybrid circuit will be to scale its dimensions to that of a state-of-the-art silicon chip and see how it compares. If it performs well, introduction in the foundries will then hinge on whether there are tough manufacturing issues associated with implementing this process. If these new channels materials make an impact, it will open up a new era for the microelectronic industry, where new functions are integrated into chips. It may not be long, for example, until the time comes when multi-core CMOS chips could communicate between cores with light via integrated III-V lasers, while making use of terahertz frequencies. So the promise of hybrid chips is awesome. However, as yet no one knows quite when – or exactly how – this is going to happen.

Further reading

C. Marchiori et. al.J. Phys. D: Appl. Phys. 47(2014) 055101 (2014)

L. Czornomaz et. al.IEDM Tech. Dig., 2.8, pp. 52-55 (2013)

L. Czornomaz,  et. al.43rd IEEE ESSDERC Proceedings, pp. 143-146 (2013)

N. Daix et. al. IEEE S3S Proceedings, in press (2013)

L. Czornomaz et. al.IEDM Tech. Dig., 24.3, pp. 517-520 (2012)

L. Czornomaz et. al.70th IEEE DRC, 207-208 (2012)

M. El. Kazzi et. al.Appl. Phys. Lett. 100063505 (2012)

L. Czornomaz et. al.Solid-State Electronics 7471 (2012)