News Article
Researchers to share insights into sub 10nm chip design
III-V layers as next generation channel materials
At the SEMICON West 2014 conference in San Francisco next week, the newly merged SUNY College of Nanoscale Science and Engineering/ SUNY Institute of Technology based in Albany, USA, will be detailing some of the research underway at its technology development centres including the use of �III-V compounds in next generation chip technology.
In his presentation 'Driving Transistor Technology Sub-10nm: Process and Equipment Direction' on the 9th July 2014,�Christopher Borst, associate professor of nanoengineering at Suny CNSE, will explain how in parallel with work developing Si nanowire devices on 300 mm wafers, CNSE researchers are evaluating III-V layers as channel materials for next generation devices.� CNSE has established an ecosystem for collaborative III-V work with industrial and research partner institutions. It is committed to developing modules for III-V gate stack, contact and source-drain engineering that are compliant with environmental guidelines while driving to device performance targets.�
Beyond III-V, CNSE is working closely with partners from academia, industry and federal research programs on 2D materials including the growth, device design, and integrated module development for these layers with a view to their �introduction into mainstream processing.� Initial successes have been made in graphene growth and transfer onto 300 mm wafer substrates for clean, repeatable processing through the CNSE development facility.
In his presentation 'Driving Transistor Technology Sub-10nm: Process and Equipment Direction' on the 9th July 2014,�Christopher Borst, associate professor of nanoengineering at Suny CNSE, will explain how in parallel with work developing Si nanowire devices on 300 mm wafers, CNSE researchers are evaluating III-V layers as channel materials for next generation devices.� CNSE has established an ecosystem for collaborative III-V work with industrial and research partner institutions. It is committed to developing modules for III-V gate stack, contact and source-drain engineering that are compliant with environmental guidelines while driving to device performance targets.�
Beyond III-V, CNSE is working closely with partners from academia, industry and federal research programs on 2D materials including the growth, device design, and integrated module development for these layers with a view to their �introduction into mainstream processing.� Initial successes have been made in graphene growth and transfer onto 300 mm wafer substrates for clean, repeatable processing through the CNSE development facility.
