GaAs: The logical successor to CMOS

BY GEOFFREY TAYLOR FROM POET TECHNOLOGIES

The end is in sight for the scaling of silicon CMOS. From the 1990s until the first few years of this millennia, simply shrinking the dimensions of silicon transistors − the only viable digital technology of the time − wrought improvements in performance that were big enough to keep pace with Moore's Law. But since 2005, the law of diminishing returns has been more relevant: Although each additional shrink has increased performance, this has been minimal, while power increases have been significant. To blame are the parasitic resistances, capacitances and inductances that have failed to scale with reductions in device dimensions. Consequently, the power per chip is constantly pushing against the acceptable limit, while the clock rate in digital systems has stalled.

To relieve these constraints, the companies that are making processors and systems-on-a-chip have pursued different paths to superior performance. They have become more creative in managing circuit performance, while adding cores, innovating with on-chip interconnect approaches and employing better cache management. In addition, they have marketed their products in new ways, switching from traditional performance metrics such as the raw core frequencies of the processor, to alternative benchmarks that showcase their efforts in a better light.

On top of this, there has been innovation by the chipmakers. Although they are not keeping pace with Moore's Law, the economics of moving to each new, smaller node can be justified, and power consumption has been kept in check by trimming the transistor's operating voltage.

An example of the pioneering efforts made by this industry has been the development of a new breed of transistor with a fin protruding out of the device. This move to a three-dimensional structure, which made its commercial debut below the 28 nm node, increases device density and cut leakage. However, these advantages come at the expense of a lower yield, and the economics is challenging for fabless companies.

In addition to these economic issues, which stem from skyrocketing tapeout and wafer costs, performance gains are diminishing with every new node introduced below 28 nm. Performance figures indicate that the core voltage has saturated at 0.75-0.80 V, preventing power reductions associated with switching between on and off states, although it has been possible to trim leakage losses.

Optical CMOS

Another avenue being pursued by the silicon industry is to introduce optical capabilities onto the silicon IC. To do this in an economically viable manner, shrinking the dimensions of the transistors on the CMOS chip must go hand-in-hand with the introduction of a technology for connecting fibre to this device.  The way forward that has attracted the most interest is that of silicon photonics: a low-loss silica waveguide connects modulators and detectors on a silicon platform. With this approach, there is the potential for CMOS drivers to co-exist on the platform.

In the past 10 years, IBM, the US government, VCs and others have spent between them more than $2 billion trying to fulfil this vision of creating optics within the CMOS IC. But even with this high level of investment − and several start-ups later "“ uniting photonics and electronics on a single chip is only a dream. Lack of progress has led to a consensus among the suppliers of optics, and the chips that drive them, that the economics dictates optics and logic in different processes − each optimized for their own function.

Despite this setback, the silicon industry is continuing its quest for a technology that will enable optical functions on the chip. This will have to be an alternative to CMOS technology, but one that is as similar to it as possible. Such a technology will prove essential as data rates migrate to 40 Gbit/s,

100 Gbit/s and then 400 Gbit/s, speeds that make the cost of packaging unmanageable. An additional requirement is that the IC will have to incorporate optical emitters and detectors. Attempts to develop such a platform that enables this transition from CMOS to optics are on-going, since no-one has yet to claim success.

Cutting power, boosting speed

To address the power and speed limitations associated with silicon CMOS, higher mobility materials must be introduced for the n and p channels. Electrons and holes can then zip through the channel faster if the voltage is maintained, or travel at speeds similar to those associated with silicon while being driven at a lower voltage "“ this latter mode of operation cuts power. To equip circuits with these new materials, the mainstream silicon industry is developing technologies to add InGaAs and SiGe channels to boost electron and hole mobility, respectively.

Figure 1. A range of devices, including the detector shown here that is formed from a HFET structure, can be fabricated with POET technology.

One option pioneered independently by imec and IBM involves the growth of InGaAs in narrow trenches etched in the silicon substrate. Although there is a high lattice mismatch, the vast majority of the dislocations that form are trapped on the sidewalls at the III-V-silicon interface. This means that there is the potential for acceptable densities at the top of the trench. However, because these trenches are very small, there can be high leakage paths along the walls between the source and the drain.

What's more, there is a very limited opportunity to vary the thickness and composition of the III-V layers that can be incorporated in the trenches, while their small size is impractical for making a laser. So it is not possible to combine high-performance InGaAs FET channels with high-performance optical emitters.

One further drawback of this approach is that the deposition of SiGe for the n-type channel requires a separate crystal growth step. Having to make two concatenated growth steps, using a rather complex process, does not bode well for acceptable yields.

An alternative approach that has been pioneered by IBM begins with the growth of III-V layers on a donor substrate. Bonding to an oxide layer transfers these high-mobility layers to a target silicon substrate. When the III-V layer is subsequently released from the donor wafer, a III-V-on-insulator structure is created on silicon. To enable the formation of p-type transistors, engineers grow an 8 nm-thick layer of SiGe on 25 nm of oxide prior to the bonding step.

Again, the fabrication of optical devices is precluded at the outset. That's because in this case the multiple layer requirements of a laser structure are too complex for a donor substrate.

There are also concerns relating to acceptable yields and costs. These arise due to the fundamentally different chemical natures of InGaAs and SiGe, which cause the etching sequences and thermal cycles for the two materials to be inherently incompatible.

Building on GaAs

Against this backdrop, POET Technologies of Toronto, ON, and Storrs, CT, is pioneering a new approach that leads to superior ICs: Planar OptoElectronic Technology (POET).  This revolutionary CMOS-friendly process IP, which enables p-channel and n-channel devices to be integrated monolithically in a III/V semiconductor environment, has the potential to fully replace all silicon-based CMOS circuitry.

By turning to strained InGaAs quantum wells with indium channels of 70 percent or more, mobility and channel velocity increase, and operation of the circuit at 0.3 V should enable a ten-fold gain in performance at 80 percent lower power compared to a silicon CMOS IC.

Development of this technology started in the early 1990s in the labs of the University of Connecticut. Since then more than 18 years has been devoted to developing and proving out numerous components of the POET platform. In 2001 we formed the start-up, and we currently have 34 patents, plus another 7 pending.

Figure 2. Injecting charges leads to a shift in the absorption edge.

Our business model is to license the III/V semiconductor process technology IP to customers and foundry partners to enable designs and produce devices that include analog, digital and optical functions on the same die for a variety of markets including, but not limited to, hand-held smartphones and tablets, PCs, servers, data centres, military and industrial applications.

With our technology, the incompatibility issue between transistors and the optical devices disappears, and it is possible to form high mobility channels for both the n-type and p-type transistors. But to do this, we have to challenge the assumption that these high-mobility materials have to be introduced on a silicon substrate.

In our case, we use substrates made of GaAs. These are currently available in diameters up to 200 mm, and there is no fundamental barrier to the production of 300 mm equivalents. Our preferred growth technique for depositing III-V layers on this foundation is MBE, and this can be applied to substrates of this size.

Tier 1 fabs already use this approach to deposit material on 300 mm wafers, so the only barrier to a switch of substrate is cost. Differences between the price of silicon and GaAs substrates will shrink as shipments of the latter rise, and costs could be further reduced through innovations in substrate release techniques. Note that the POET fabrication process employs the same set of foundry tools currently used for silicon CMOS, so only a reconfiguration is required.

The idea of using GaAs rather than silicon to make digital circuits is not new. During the nMOS era that spanned the 1970s and early 1980s, GaAs MESFET technology was a contender for silicon E/D logic applications. And later, during the development of CMOS, the GaAs HEMT was also considered for high-speed logic circuits.

Two fundamental flaws prevented these GaAs devices from making a significant impact. The first is that both the MESFET and the HEMT are inherently normally on (depletion) devices, and although the threshold can be shifted marginally to the positive, the swing is too small to be well controlled. The second is that it is not possible to make p-channel MESFETs and HEMTs, which prevents the construction of a complementary technology.

Our POET technology is not held back by these issues. In our case, the p-type form of the FET is a natural component in the POET device family. Although the pFET and the nFET are grown as enhancement devices, they can be transformed to depletion devices with a suitable implant. Consequently, the complementary inverter is just as compact as it is when built with silicon CMOS technology, but it can operate with a smaller supply voltage.

All of the devices in the POET family are formed with a single epitaxial growth step that creates multiple-quantum-well or multiple-quantum-dot layers. This is followed by a comprehensive fabrication sequence, which produces electronic and optical devices simultaneously.

Electronic devices are realized as bipolars, FETs and thyristors. For the HFETs, gates are formed by refractory metals, with the multiple quantum wells becoming the channels of n-type and p-type devices, and self-aligned ion implants defining the source and drain regions. Like MOSFETs, the HFETs have a back gate contact, which is the substrate.

Figure 3. POET technology can be used to create a complementary inverter, a key building block for an IC.

The gate metal of the HFET forms an ohmic contact. This eliminates static conduction because the gate input logic swing is always maintained below the knee voltage of the input diode. In contrast, both the pnp and npn bipolars are in the form of bipolar inversion channel transistors (BicFETs), with the refractory ohmic contact behaving as the emitter terminal operating in the conductive region.

Meanwhile, in the bipolar devices, the multi-quantum well channels function as control electrodes, while the collectors are quantum-well regions contacted by ion implantation. Finally the thyristor utilizes both HFETs and BicFETs. This four-terminal digital device has a high resistance off-state and a low resistance on-state, which makes it useful in synchronous circuits and memory applications.

The same sequence of steps creates optical devices. To form a quantum-well laser from the HFET structure, the refractory emitter is contacted and also the channel. Laser operation is possible with either p-type or n-type contacts. Note that it is also possible to operate the thyristor as a laser when it is switched to its conducting state.

Thanks to the flexibility of the POET platform, lasers can be produced as either in-plane emitters or VCSELs. To fabricate the latter class of device, the transistor structure has to be designed to fit within an integer number of half wavelengths. This requirement is easier to fulfil when the laser operates at longer wavelengths, such as those around 1.5 mm. For an in-plane laser, the preferred implementation is a closed loop resonator.  Output is directed into a straight waveguide, which has losses that are trimmed through novel implant techniques.

Figure 4. Transfer characteristics of a cHFET complementary invertor formed with POET technology.

One of the strengths of this design is the great flexibility of the resonator: It can be varied from a large perimeter, rectangular design that features conventional wave-guiding for increased laser output power to a small perimeter circular resonator, which is based on whispering gallery mode (WGM) wave-guiding, and delivers a greatly reduced output power. These structures are ideal for optical filtering, wavelength-division multiplexing operations and slow light control.

It is also possible to build absorption modulators, detectors and optical amplifiers from the HFET structure used for the laser. Typically, these are implemented in a linear waveguide geometry, because a cavity is not required (see Figure 1). However, it is essential to control the absorption profile via the applied voltage, because this enables voltage control of the refractive index. With the POET platform this requirement is met, because injection of charges leads to a blue shift in the absorption edge (see Figure 2).

Conventional processes

We produce our devices by MBE, the only deposition process providing precision doping, thickness control and laser quality. This particular epitaxial process is also unmatched in its ability to realize self-assembled quantum dots. To trim growth times, we use various approaches, such as the deposition of top mirrors.

Figure 5. An integrated transmitter (a) and receiver (b) formed with POET technology.

The fabrication processes that we employ are very similar to those associated with silicon CMOS. For both n-type and p-type FETs, sputtering forms the refractory gates. After etching close to the quantum wells, ion implantation defines the source and drain regions and the laser apertures for VCSEL current steering. High-temperature annealing follows, before implants are metalized and interconnected.

Addition of the metal enables electrical devices, and also allows injection and extraction of carriers in a variety of optical waveguide devices, including detectors, modulators, amplifiers and directional couplers. Etching through to the bottom mirror isolates all devices.

When we started our development effort, we used a 1 mm gate size, but more recently we have scaled to 100 nm. Currently nFETs with an effective gate length of 0.6 mm and a cut-off frequency of 42 GHz.

Structures that we have made include an inverter (see Figure 3 for an example). This device can exhibit the ideal behaviour required for complementary operation (see Figure 4). Other efforts by us include integration of the laser and the detector to form the transmit and receive functions in a vertical cavity format (see Figure 5).

Our development programme has enabled stabilisation of the fabrication and growth platform, and we are now in a position to develop a full suite of optoelectronic devices. We can now fabricate logic blocks based on cHFET designs, while simultaneously developing optical input/output blocks, which require novel spot-size converters to realise low insertion loss to/from fibres in a low-cost package.

Further scaling of our device portfolio is required. That should not prove too tricky, as based on our preliminary work on logic devices with 100 nm feature sizes, it is clear that the our devices will also scale down to 15 nm and even 10 nm − just as silicon is doing now.

While scaling is important, it is by no means our only goal. It turns out that the modulation-doped interface formed with our technology, which is a normally off channel, is ideal for the implementation of the single electron transistor. This form of transistor can access engineered quantum dots at the interface, which have quantum levels differentiated by spin. It is possible that these single electron transistors could aid the development of quantum computing, with electron spin providing the quantum variable to form quantum computing logic blocks.

Thus our POET technology could provide a chip environment for conventional logic and optoelectronics that serves the computers of today, while providing a bridge between the quantum computing function with qubits and the real world of classic logic with its binary numbers.