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Japanese group reduces defects in SiC transistors

Dielectric film growth technique could improve next generation SiC power devices

A research group at the University of Tokyo Graduate School of Engineering has found a way to reduce defects in silicon carbide devices to improve performance.

SiC devices offer the potential for lower energy loss than conventional silicon devices, but SiC transistors suffer from high resistance and low reliability, mainly due to defects formed at the interface between SiC gate dielectric film. Such defects, caused by impurities and atomic excess or deficiency at the interface, need to be reduced to improve the performance.

The Tokyo University group led by Koji Kita found that the density of interface defects is significantly reduced by employing reaction conditions where the by product carbon is ejected as carbon monoxide when creating the gate dielectric film. The group achieved the lowest defect density in a metal-oxide-semiconductor test structure employing these conditions.


The diagrams above show: (left) a schematic of oxidation of SiC/SiO2 interface; and (right) Interface state density of 4H-SiC/SiO2 observed in this study, compared with previously reported typical values (hatched areas). The horizontal axis shows the energy levels of defect states referred to the conduction band edge of SiC.
 

This technique provides a high quality SiC interface without any extra processes such as addition of nitrogen-containing gases, assuring the easy industrial application of this method. This technique is expected to improve the performance and accelerate the spread of SiC power devices, contributing to energy saving in a variety of applications, including electric power transmission, electric vehicles, and factory machines.

The work was published as "Fabrication of SiO2/4H-SiC (0001) Interface with Nearly-Ideal Capacitance-Voltage Characteristics by Thermal Oxidation" by Richard Heihachiro Kikuchi and Koji Kita, in Applied Physics Letters 105, 032106 (2014).
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