Technical Insight
III-Vs prepare to replace silicon
Record mobilities, production processes on 300 mm silicon and impressive nanometre-scale performance indicate that III-V MOSFETs are getting closer to enter production
RICHARD STEVENSON REPORTS
For many years, pundits have argued that the shrinking of silicon is about to come to an end. Often, though, thanks to unforeseeable innovations by the engineers in the labs and fabs, obstacles have been overcome and the march of Moore's Law has prevailed.
But now, arguably more than ever before, it seems that the days of silicon really are numbered. After all, why else would the silicon heavyweight IBM agree to pour $3 billion into the development of new technologies, including post-silicon materials for the 7 nm node and beyond?
The leaders of IBM view several materials as possible successors to silicon, including compound semiconductors. III-Vs sport high electron mobility, and if they could be used in the channel of post-silicon MOSFETs, they would enable devices to deliver a high current at a lower operating voltage. This would ultimately underpin a trimming of the power per transistor as size is reduced, one of the trends associated with Moore's Law that is now under threat.
Efforts at developing compound semiconductor MOSFETs were discussed at the most recent VLSI Symposium, which was held in Honolulu, Hawaii, from 9-13 June 2014. At this meeting a team headed by researchers at the Korea Advanced NanoFab Centre (KANC) claimed a new record for mobility in a III-V MOSFET; engineers from imec reported the development of foundry-compatible process for making compound semiconductor finFETs on 300 mm silicon; and a team led by researchers at the University of California, Santa Barbara (UCSB), claimed to have produced the first III-V MOSFETs that can match or exceed those of production silicon devices, while being constructed at dimensions relevant to the VLSI industry.
Record mobilities
Researchers at KANC, working in partnership with those at Yonsei University, Sematech and GlobalFoundries, announced at the conference a claim for record effective mobility of more than 5500 cm2 V-1 s-1, using a III-V MOSFET incorporating an In0.7Ga0.3As channel.
Chan-Soo Shin from KANC, speaking on behalf of the team, attributes the record to a combination of a high-indium-content InGaAs channel, MOCVD selective source and/or drain re-growth, and a gate-last integration scheme.
By employing a gate last process, the heart of the device is not subjected to high temperatures.
"Unlike silicon, the interface quality of an oxide-and-indium-gallium arsenide interface tends to be easily deteriorated when it experiences processes with temperatures above 500 °C," says Shin. Such temperatures are common in the conventional gate-first approach, with source and drain implantation-activation typically taking place at more than 800 °C, and raised source and drain re-growth processes occurring at 600 °C. But at these elevated temperatures, gallium atoms diffuse out of the InGaAs channel, impairing interface quality and carrier transport.
The team has optimised its composite gate stack, which has a thin, passivation layer of Al2O3 and a layer of HfO2. According to Shin, this pairing produces good values for the equivalent oxide thickness, and can combine with InGaAs to produce a low density of interface states.
Figure 1: Researchers from KANC, working in partnership with those at Yonsei University, Sematech and GlobalFoundries, produced
a MOSFET with a gate-last process that delivered an effective mobility of more than 5500 cm2 V-1 s-1.
MOSFETs produced by the partnership were formed by first growing an In0.52Al0.48As barrier and a 10 nm-thick In0.7Ga0.3As channel on a semi-insulating InP substrate (see Figure 1). MOCVD re-growth formed heavily doped contacts for source and drain, prior to mesa isolation, the addition of ohmic contacts for the source and drain, and atomic layer deposition of 0.7 nm of Al2O3 and 3 nm of HfO2 to form the gate stack (see Figure 2). Devices were constructed with gate lengths ranging from several microns to 22 nm.
Figure 2: Cross-sectional transmission electron microscopy images of structures produced by the team led by researchers from KANC. These images show the photoresist, HSQ, and the dummy gate, for gate lengths of 1 µm (a) and 22 nm (b). High-resolution images offer insights into the quality of the interface between the In0.3Ga0.7As channel and the regrown GaAs (c), and the Al2O3/HfO2 gate stack on the InGaAs/InAlAs quantum well.
Effective electron mobility for a device with a 5 µm gate exceeded 5500 cm2 V-1 s-1 at 300K (see Figure 3), and with a source-drain voltage of 0.5 V, this MOSFET had excellent electrostatic integrity, including a sub-threshold swing of 80 mV/decade and a drain-induced barrier lowering of 22 mV/V.
Figure 3: The surface-channel MOSFET produced by KANC produces very high mobility, while having a low equivalent oxide thickness.
Shrinking device dimensions led to a deterioration in electrostatic integrity. At a gate length of 40 nm, sub-threshold swing and drain-induced barrier lowering climbed to 105 mV/decade and 150 mV/V, respectively, and at 22 nm they hit 250 mV/decade and 450 mV/V.
Shin blames the deterioration in performance at shorter gate lengths on short-channel effects, which could be addressed by switching to a three-dimensional channel architecture. "When and if InGaAs is introduced into silicon foundries, it will be somewhere around the 7 nm technology node or beyond. In those regimes, the transistor architecture should be non-planar, such as a three-dimensional channel or gate-all-around, to guarantee electrostatic integrity."
If the technology developed by the team is to make a commercial impact, production of the devices will have to be transferred to 300 mm silicon substrates.
"There are a couple of options, such as wafer-bonding, a blanket approach using a metamorphic buffer, and aspect-ratio trapping," says Shin, who reveals that the team's preferred approach is the latter one. "We really want to use a small area on silicon, where III-Vs are defined selectively, adjacent to other devices, such as silicon CMOS and/or germanium PMOS," says Lee. "Also, III-V materials grown by aspect-ratio trapping are known to be ideally defect-free on the top portion, enabling an overcoming of lattice mismatch issues."
III-Vs on 300 mm silicon
Leading development of aspect-ratio trapping processes for forming III-Vs on large silicon wafers is imec, a microelectronics research centre in Leuven, Belgium. At the VLSI Symposium, researchers from there unveiled the results of efforts to transfer their replacement fin process from
200 mm to 300 mm silicon.
"In the end it was a smooth transition as all the learning from the 200 mm tools for the other process steps was directly transferrable to 300 mm," says Niamh Waldron. "Likewise, there is no fundamental issue with transferring it to 450 mm silicon."
Fabrication of the team's InGaAs/InP quantum-well finFETs began by taking standard shallow-trench isolation templates, and etching out the silicon to form trenches (see Figure 4). Selective growth of III-Vs in the silicon-lined trenches followed. Although defects are generated due to lattice mismatch, these imperfections propagate towards the sidewalls and annihilate there, so there is relatively high material quality near the top of the trench.
Figure 4: Researchers at imec employ aspect-ratio-trapping technology to create III-V MOSFETs on silicon with a high-quality InGaAs channel.
Formation of the finFET fabrication began by depositing InP in the trench, smoothing the surface with chemical mechanical polishing and etching away a little InP. InGaAs was then deposited in this recess, before the surface wass smoothed again with chemical mechanical polishing, and areas beside the trench were etched away with SiCoNi to produce a protruding fin (see Figure 5).
Figure 5: A dark-field, scanning tunnelling electron microscopy image of the InGaAs channel formed by imec's engineers. The inset is a transmission electron microscopy image of the gate stack.
"Controlling the damage to the III-V during etch is not a fundamental issue, but does require optimisation," says Waldron. "We are currently working with our partners on both the replacement fin process "“ which does not require a fin etch "“ and also an etched fin approach."
Like the team involving researchers from KANC, Waldron and co-workers used a gate-last process to temper intermixing at the interface between the channel and the dielectric.
Another noteworthy aspect of imec's approach is the use of a magnesium dopant for both the InP buffer and the InGaAs channel. Metal organics used to form these layers are carbon rich, and when carbon is present in nominally undoped InP, it leads to excessively high source-drain leakage. By introducing magnesium, imec's engineers have formed p-type InP that not only slashes leakage currents, but also increases the conduction band offset with the channel layer, thereby increasing carrier confinement.
Engineers formed devices with an 30 nm-thick InGaAs channel and a 50 nm fin. For doped buffers, leakage is cut by increasing the doping in the channel "“ and improvements are more pronounced for lightly doped buffers. If the channel is undoped, leakage currents plummet with highly doped InP, thanks to up-diffusion of magnesium from the buffer to the channel during growth and processing. A doped channel is bad news, because carrier mobility declines. By applying conditions that offer the best compromise between leakage current and mobility, devices can realise a saturated sub-threshold swing of 190 mV/decade.
"While magnesium doping is effective at reducing the off-state leakage, it does impact electron mobility and device performance, so we are pursuing device designs that need lower or no magnesium doping," comments Waldron. Efforts are also being directed at achieving a low defect density in the III-V layer when the process is scaled to 10 nm or 7 nm.
Superior scaling
Meanwhile, researchers at UCSB are claiming to have fabricated the first III-V MOSFETs that have on-current, off-current and operating voltages comparable to or exceeding production silicon devices "“ while being constructed at dimensions that are relevant to the VLSI industry.
Devices produced by the team, which is led by Mark Rodwell, Arthur Gossard and Susanne Stemmer, have a 25 nm gate length, can operate at 0.5 V, and produce an on-current of 0.5 mA and an off-current of 100 nA/µm.
To set a new benchmark for III-V MOSFET performance, modifications to the conventional device architecture included a trimming of the InAs channel thickness to just 2.5 nm. Sanghoon Lee from the team told Compound Semiconductor that the thinner channel aids the off-state current because it increases the quantised band gap of the InAs quantum well, leading to a reduction in band-to-band tunnelling, which is likely to happen near a high drain field region. Another benefit of a thinner channel is an increase in gate capacitance, which could help boost on-current.
The high-performance of these MOSFETs has been aided by the development of a high-quality gate insulator, made from the pairing of Al2O3 and ZrO2.
"We have used zirconium oxide instead of hafnium dioxide, because MOS capacitor analysis for zirconium oxide verses hafnium dioxide tells us that the permittivity of zirconium oxide, typically 23, is larger than that of hafnium dioxide, 19," explains Lee. However, the total gate capacitance would not increase by much if ZrO2 was replaced by the more common HfO2. According to Lee, that's because it is the semiconductor capacitance in the III-V MOSFET, rather than the oxide capacitance, that is the limiting factor for the total gate capacitance.
Due to this, Lee argues that the impressive performance of the MOSFET is essentially down to the insertion of a thin channel, plus the introduction of a vertical spacer that leads to a smoother distribution of the field within the device. By ironing out the spikes in the electric field profile, band-to-band tunnelling is prevented and leakage currents are reduced.
MOSFETs were formed from epistructures grown by MBE on semi-insulating InP. After depositing a 50 nm-thick unintentionally doped InAlAs buffer, engineers added: a 250 nm-thick, p-doped InAlAs barrier; an unintentionally doped 100 nm-thick InAlAs barrier; a 2 nm-thick InAlAs n-type, pulse-doped layer; a 5 nm-thick unintentionally doped InAlAs setback; a 3.5 nm-thick strained InAs channel; and a 2 nm-thick, unintentionally doped In0.53Ga0.47As spacer (see Figure 6).
Figure 6: The vertical spacer and the thin InAs channel are claimed to hold the key to the high-performance of the UCSB MOSFET.
Dummy gates with lengths ranging from 12 nm to 1000 nm were formed by coating wafers with a 20 nm-thick film of the photoresist hydrogen silsesquioxane, and patterning the surface with electron-beam lithography. MOCVD added the remainder of the 12 nm-thick spacer and heavily doped In0.53Ga0.47As regions for the source and drain.
Using MBE processes for the creation of epiwafers for VLSI is not ideal, due to high costs and the challengers of growing uniform films over large wafers. "The reason why we are using MBE is that our MOCVD system has no aluminium source, so we cannot grow the indium aluminium arsenide barrier using MOCVD," explains Lee. "To my best knowledge, InP-related material can be grown using MOCVD that is as good as MBE, in terms of epi-quality."
To process the epiwafers into MOSFETs, device mesas were defined with a wet etch, before dummy gates were stripped in buffered hydrofluoric acid. A two-cycle isotopic digital etch then removed about 2 nm of the In0.53Ga0.47As cap and about 1 nm of the InAs to leave a 2.5 nm-thick channel. These wafers were immediately loaded into an ALD tool.
After in-situ nitrogen plasma/tri-methyl-aluminium treatment led to the formation of a 0.7 nm thick layer of Al2OxNy, a 3 nm-thick ZrO2 gate dielectric was deposited. MOSFETs were ready for testing after subsequent annealing at 400 °C, plus the creation of a Ni/Au gate and source and drain contacts formed from a Ti/Pd/Au stack. Transistors with a 25 nm gate length produced a peak transconductance of 2.38 mS/µm at a drain-source voltage of 0.5 V. Operating at a voltage of 0.5 V for the drain (VDD), the device produced an on current of 0.5 mA/µm (see Figure 7) and an off-current of 100 nA/µm. Sub-threshold swing was just 72 mV/decade at a drain-source voltage of 0.1 V, rising to 77 mV/decade at 0.5 V.
Figure 7: The MOSFET from UCSB sets a new benchmark for on-current at short gate lengths.
Lee believes that even though the silicon industry has recently moved to three-dimensional, finFET structures, when III-Vs are introduced into the channel, there could be a move back to planar devices, such as their MOSFET. "III-V materials are vulnerable to dry-etch damages," argues Lee, "so it might be very difficult to get fins using current dry etch techniques. In addition, planar processes could be more cost-effective."
Devices produced by the team were designed for high-performance applications, which require an off-state leakage current below 100 nA/µm. Even lower values of 1 nA/µm and 30 pA/µm must be met for standard and low-power performance, and Lee and co-workers are aiming to address these requiremnets by modifying the channel and vertical spacer.
Efforts by this team, plus those at imec and KANC, are clearly closing the gap between the state-of-the-art of the III-V MOSFET and the characteristics it requires to make an impact in the foundries. As time goes on, this gap should continue to shrink "“ but will it be at sufficient speed to allow compound semiconductors to make an impact at the 7 nm node?
