TowerJazz and UCSD show 60GHz Wafer-Scale Phased Array Transmitter
Specialist foundry TowerJazz and the University of California, San Diego (UCSD) have demonstrated a 256-element (16 x 16) wafer-scale phased array transmitter with integrated antennas operating at 56-65GHz.
The chip was built on TowerJazz's 0.18µ SiGe BiCMOS process, SBC18H3, and the collaboration partially funded through the DARPA DAHI (Diverse Accessible Heterogeneous Integration) Program.
The phased-array system-on-a-chip (SoC) targets the emerging 5G high-performance wireless standard which will aim for greater than 10Gbps peak data-rate communication. The array has beamforming capabilities that include independent amplitude and phase control for all 256 different antenna elements.
Phased arrays allow the electronic steering of an antenna beam in any direction and with high antenna gain by controlling the phase at each antenna element. The radiation beam can be "˜moved in space' using entirely electronic means through control of the phase and amplitude at each antenna element used to generate the beam.
This steering technique is more compact and faster than mechanically steered arrays. Furthermore, phased arrays allow the creation of deep nulls in the radiation pattern to mitigate strong interference signals from several different directions. They have been in use since the 1950s in defense applications and have seen limited use in commercial systems due to their relatively high cost.
By developing this wafer-scale chip, UCSD and TowerJazz hope to reduce the cost of phased arrays especially at millimeter-wave frequencies for 5G communication systems.
"We have a track record of successful collaboration with TowerJazz and the ability to bring this innovative design from UCSD to market depends strongly on TowerJazz's SiGe BiCMOS foundry process which enables lower-cost phased arrays through integration of multiple circuit functions and high efficiency antennas on the same silicon chip," said Gabriel M. Rebeiz, distinguished professor of electrical engineering at UCSD, the lead professor on this chip.
"We believe the results achieved by UCSD's 5G 60GHz phased array transmitter again demonstrate the remarkable teamwork between TowerJazz, UCSD and DARPA, to provide novel capabilities and technologies to both the aerospace and defense community as well as commercial markets," said David Howard, TowerJazz's executive director and fellow and co-principal investigator for the DARPA DAHI Program.
SBC18H3 BiCMOS process
TowerJazz's SBC18H3 process offers both 0.18-micron SiGe bipolar and passive elements combined with 0.18-micron CMOS, to enable high-speed networking and millimeter wave applications.
The process offers SiGe transistors with peak Fmax of 280GHz and peak Ft of 240GHz, suitable for low-power, high performance millimeter wave circuits, which replace the need for more expensive GaAs chips. SBC18H3 comes standard with 1.8 and 3.3V CMOS (dual-gate), deep trench isolation, lateral and vertical PNP transistors, MIM capacitors, high-performance varactors, poly-silicon as well as metal and N-well resistors, PIN and Schottky diodes, high-Q inductors, triple well isolation, and six layers of metal. TowerJazz also manufactures a faster, lower noise process, named SBC18H4, with Fmax of 340GHz.
The chip was designed and tested by Samet Zihir and Ozan Gurbuz from the electrical and computer engineering department at UCSD under the supervision of Gabriel M. Rebeiz, with help from Arjun Karroy, TowerJazz, and was sponsored by the DARPA DAHI program under the direction of Daniel Green.
UCSD's phased array SoC
The wafer-scale 256-element SiGe BiCMOS SoC phased-array is 42x42 mm2 and combines the 60GHz source, amplifiers, distribution network, phase shifters, voltage controlled amplifiers, and high-efficiency on-chip antennas (16 x 16 elements), allowing record performance for a new generation of high-performance phased arrays for the 60GHz band (56-65GHz).
Such an advancement better serves the needs of the greater than $500M emerging market of 5G 60GHz base-stations with beamforming capabilities and Gbps data rates. The antennas are integrated on-chip, which removes the expensive and lossy transitions and distribution network between the phased array and the off-chip antennas.
This wafer-scale phased array with 256 radiating elements, together with all the necessary CMOS control circuits such as dual SPI control (serial parallel interface), is capable of electronic beam scanning to +/-50 degrees in all planes - the most of any mm-wave phased-array antenna to date. A measured EIRP (equivalent isotropically radiated power) of 45dBm at 60GHz was achieved from the wafer-scale array at an operating temperature of 95-100degC, congruent with basestation temperatures, and within the FCC's EIRP power limits for 60GHz band. The architecture could be scaled to 512 (16x32) or 1024 (32x32) elements due to on-chip antenna integration and the wafer-scale integration of multiple reticles on a single chip.
