Technical Insight
Removing thermal barriers to GaN HEMTs
Power densities produced by GaN HEMTs can reach their full potential by integrating these devices with diamond and microfluidic cooling
BY MATTHEW TYHACH AND DAVID ALTMAN FROM RAYTHEON
The GaN revolution is well underway, with the performance of RF systems on the rise, but ultimately limited in its full potential by thermal impediments. That's because while generating high RF output powers for signal transmission, GaN power amplifiers dissipate a commensurately large amount of power in the form of heat in the transistor and the chip area. More than 100 W of power can be dissipated by the chip, creating localized transistor hot spots with fluxes above 10 kW cm-2 and package-level volumetric heat generation that can exceed 100 W cm-3.
Levels of power dissipation are so high that they are challenging the capabilities of conventional approaches to thermal management. It is no longer sufficient to prevent a device from overheating by positioning carefully selected materials nearby, and using them to transport heat to a local heat exchanger.
So great are the concerns of overheating that engineers are throttling back the operating voltage of the GaN HEMT and are also increasing its physical area. Such schemes limit channel temperatures to the desired operating region. An enhanced thermal management strategy would enable engineers to operate GaN HEMTs at higher voltages and in smaller areas, lowering the cost of an RF system on a cost-per-Watt basis, and opening the door to new systems that deliver more RF power while retaining their area. At Raytheon we are researching this front under funding from the DARPA Intrachip/Interchip Enhanced Cooling (ICECool) programme. Our efforts have focused on developing a high-performance thermal management architecture. We replace a conventional GaN HEMT with one that features a high-conductivity CVD diamond substrate for enhanced heat spreading, and subterranean microchannels that improve heat removal.
With this design, material with the highest thermal conductivity known to man is positioned right underneath the GaN HEMT channel hot spot, and heat is extracted very efficiently by integrating the heat exchanger directly into the device's substrate. Thanks to these advances in thermal management, the power handling capability of today's GaN HEMTs can increase five-fold, enabling amplifiers to operate at far higher power densities. This breakthrough ultimately has the potential to underpin yet another revolution in RF performance without inventing a new semiconductor technology.
Diamond and microfluidics
The GaN revolution is well underway, with the performance of RF systems on the rise, but ultimately limited in its full potential by thermal impediments. That's because while generating high RF output powers for signal transmission, GaN power amplifiers dissipate a commensurately large amount of power in the form of heat in the transistor and the chip area. More than 100 W of power can be dissipated by the chip, creating localized transistor hot spots with fluxes above 10 kW cm-2 and package-level volumetric heat generation that can exceed 100 W cm-3.
Levels of power dissipation are so high that they are challenging the capabilities of conventional approaches to thermal management. It is no longer sufficient to prevent a device from overheating by positioning carefully selected materials nearby, and using them to transport heat to a local heat exchanger.
So great are the concerns of overheating that engineers are throttling back the operating voltage of the GaN HEMT and are also increasing its physical area. Such schemes limit channel temperatures to the desired operating region. An enhanced thermal management strategy would enable engineers to operate GaN HEMTs at higher voltages and in smaller areas, lowering the cost of an RF system on a cost-per-Watt basis, and opening the door to new systems that deliver more RF power while retaining their area. At Raytheon we are researching this front under funding from the DARPA Intrachip/Interchip Enhanced Cooling (ICECool) programme. Our efforts have focused on developing a high-performance thermal management architecture. We replace a conventional GaN HEMT with one that features a high-conductivity CVD diamond substrate for enhanced heat spreading, and subterranean microchannels that improve heat removal.
With this design, material with the highest thermal conductivity known to man is positioned right underneath the GaN HEMT channel hot spot, and heat is extracted very efficiently by integrating the heat exchanger directly into the device's substrate. Thanks to these advances in thermal management, the power handling capability of today's GaN HEMTs can increase five-fold, enabling amplifiers to operate at far higher power densities. This breakthrough ultimately has the potential to underpin yet another revolution in RF performance without inventing a new semiconductor technology.
Diamond and microfluidics
One of the great strengths of GaN-on-diamond is that it unites high-thermal conductivity CVD-grown diamond with GaN that is commercially available in production today. GaN-on-diamond substrates are created by removing the original substrate for GaN epitaxial growth "“ it could be silicon, sapphire, or SiC "“ and replacing it with CVD diamond through a direct diamond growth process (Figure 1).
Figure 1. GaN epitaxial material is transferred from its growth substrate to a diamond substrate.
To realise this, a protection layer is added to the topside of the GaN, and this is then bonded to a physical handle wafer. The protection layer allows removal of the handle wafer at the end of the process without damaging the GaN. Following substrate removal, a thin nucleation layer is applied prior to the growth of the diamond layer. This means that diamond is located just a few microns from the GaN hot-spot. The diamond dramatically improves heat spreading, thanks to a conductivity that is three times that of SiC. The pioneer of this process is Group4 Labs, since acquired by Element 6. Over the years, wafers have increased in diameter and yield, and 100 mm material is now available (see Figure 2, below).
Figure 2. 100 mm GaN-on-diamond wafer after fabrication (left) and GaN-on-diamond with microchannel cooling (right).
To increase thermal performance over conventional systems that use either air cooling or fluidic cooling further downstream, we adopt a microfluidics technology that positions the heat exchanger very close to the diamond substrate. This is realised with high-aspect ratio diamond microchannels that are filled with a standard coolant (see Figure 2, right). Performance is optimised by placing the channels next to the hot spots of the GaN-on-diamond MMIC, and using a silicon manifold layer to regulate the direction, flow rate, and pressure of the coolant.
Measurements on an RF MMIC will ultimately highlight the capability of the combination of GaN-on-diamond and microfluidic cooling. Operating at the same temperature as a state-of-the-art GaN-on-SiC MMIC, our design models suggest an RF output power that is 4.9 times higher than our baseline MMIC. Superiority stems from an increase in MMIC periphery by a factor of 4.2 over the baseline, as well as a 50 percent increase in bias voltage (see Table 1). Note that the added periphery does not lead to an increase in the size of the MMIC because the gate-to-gate spacing within the transistor layout is shrunk by a factor of 4.
Measurements on an RF MMIC will ultimately highlight the capability of the combination of GaN-on-diamond and microfluidic cooling. Operating at the same temperature as a state-of-the-art GaN-on-SiC MMIC, our design models suggest an RF output power that is 4.9 times higher than our baseline MMIC. Superiority stems from an increase in MMIC periphery by a factor of 4.2 over the baseline, as well as a 50 percent increase in bias voltage (see Table 1). Note that the added periphery does not lead to an increase in the size of the MMIC because the gate-to-gate spacing within the transistor layout is shrunk by a factor of 4.
Table 1. Comparison of the key parameters between today's MMIC and the ICECool Demonstration MMIC.
Conversion of the baseline design to a higher power MMIC began with consideration of the differences in electrical properties between SiC and diamond substrates. The baseline features co-planar waveguide transmission lines, formed on the substrate top surface by a centre-line surrounded by two ground planes. Measurement and modelling of test structures on diamond wafers revealed that CVD-grown diamond has an effective dielectric constant of 5.70, compared with 10.03 for SiC. A major impact of this difference is that the length of the transmission lines must be longer on diamond than on SiC to achieve the same electrical impedance.
Another focus of our work has been the optimisation of the location of microchannels in the substrate, to ensure maximum thermal and electrical performance. By minimizing the channel temperature and transmission line insertion loss, we increase the power-added efficiency of the MMIC.
We have used ANSYS for high-frequency electromagnetic field simulation to investigate the impact of fluid-filled microchannels in the substrate on transmission line performance. These calculations allowed us to optimise the electrical placement of the microchannels (see Figure 3). Efforts began by varying the clearance depth from the top transmission line conductor surface to the top of the microchannel in the substrate. Calculations considered a baseline of no channel, and depths of up to 80 µm.
Figure 3. The ANSYS tool for high-frequency electromagnetic field has been used to assess microchannel placement (green) underneath co-planar waveguide transmission lines and the ground plane (orange).
Results from these simulations reveal that a clearance of just 5 mm has a significant impact on insertion loss and impedance, while a depth of 80 mm has minimal effect at our frequency range of interest, which is X-Band (8 GHz -12 GHz) and below (see Figure 4, left). Setting clearance at 80 mm, we then analysed variable locations of the microchannels relative to the edge of the top transmission line and ground conductor surfaces, and varied the lateral setback by up to 50 mm. Results show that locating the microchannels underneath a conductive surface with any setback effectively negates any influence from having microchannels in the substrate. These insights led us to position the microchannels so that they are setback into the conductor surfaces and have a minimum clearance of 80 µm.
Figure 4. The ANSYS tool for high-frequency electromagnetic field simulations has provided insight into: transmission line with microchannel placement while varying depth underneath the conductor surface (left): and microchannel placement 80 µm below the conductor, while varying lateral setback from the conductor edge (right).
Production challenges
Today, GaN-on-diamond wafers present unique challenges for wafer processing foundries to create high-yielding and high-performance HEMTs and MMICs. One particular challenge arising from the unique properties of this engineered substrate is wafer bow. As growth of diamond occurs at high temperatures while the GaN is attached to the silicon handle wafer, distortion results during post-growth cooling, due to differences in thermal expansion coefficients (see Figure 5).
Figure 5. The mismatch in the coefficient of thermal expansion of silicon and diamond causes the wafer to bow as it cools from the growth temperature to room temperature.
Another difference is that GaN-on-diamond wafers are thinner than commercially available GaN wafers, so that the increased cost of growing diamond is partially offset. Due to this, GaN-on-diamond wafers tend to be incompatible with the focal length range of most production lithography tools. To address all these issues, a supporting carrier wafer is bonded to the underside of a GaN-on-diamond wafer to reduce its bow and increase its height.
Another difference is that GaN-on-diamond wafers are thinner than commercially available GaN wafers, so that the increased cost of growing diamond is partially offset. Due to this, GaN-on-diamond wafers tend to be incompatible with the focal length range of most production lithography tools. To address all these issues, a supporting carrier wafer is bonded to the underside of a GaN-on-diamond wafer to reduce its bow and increase its height.
Fortunately, carrier wafers are not unique to semiconductor fabrication "“ they are already used in back end of line processing. However, the big difference with a GaN-on-diamond wafer is that a carrier wafer is needed for the entire fabrication sequence. This means that the bond to the carrier must be able to withstand all foundry chemicals and a wide range of temperatures, while still allowing release of the GaN-on-diamond wafer once fabrication is complete. On top of these restrictions, the carrier material must be stiff enough to reduce the bow of the GaN-on-diamond wafer; and it must have a thermal coefficient of expansion that is close to that of diamond, so that it does not unintentionally demount at higher temperatures during the fabrication process.
Fulfilling all these requirements narrows the selection of bonding materials and carrier wafers. We have identified what is suitable and have developed a bonding process that permits the mounting of GaN-on-diamond wafers in a manner that is compatible with high-resolution lithography.
Following completion of front-side fabrication, backside processing is undertaken, including the formation of microchannels for fluidic cooling. So far, we have worked with co-planar waveguide transmission lines, but we are also developing a backside process for forming through-substrate vias that will enable electrical grounding of designs incorporating microstrip transmission lines.
Etching diamond is required to form these microchannels and electrical grounding vias. This process is not trivial, because diamond requires different etchants from SiC, and fabricating patterned features requires novel masks that are not damaged or eroded during the etching process. Complicating matters even further, CVD diamond substrates tend to have a far higher degree of roughness than those made from crystalline silicon and SiC, so special consideration must be given to substrate preparation prior to etching. The good news is that we have demonstrated these unique backside processes that address the particular novel challenges associated with GaN-on-diamond wafers (see Figure 6).
Figure 6. Diamond wafer backside surface before (left) and after (right) polishing and via formation.
Although the manufacture of our novel GaN HEMTs will require some new approaches, we have developed processes that address issues associated with wafer bow, wafer thickness, backside roughness and diamond etching. Our five-fold gain in performance through improved thermal management is revolutionary, and GaN MMICs operating at higher power densities should follow, as tools, processes and materials to make these devices are now in place.
