Showcasing the compounds at VLSI

For a decade or more, our community has devoted much effort to the development of III-V transistors for maintaining the march of Moore's Law. It has been argued that armed with a superior mobility to silicon devices, those made from compound semiconductors can operate at a lower voltage while maintaining current, and thus enable power scaling at future nodes.

Progress of these devices is continuing, with some of the latest breakthroughs reported at the 2018 Symposium on VLSI Technology and Circuits, held in late June in Honolulu, HI. At that gathering, where there were also reports of progress associated with III-V photodetectors, highlights included talks on: tunnel FETs made from InGaAs and GaAsSb with a sub-threshold swing that broke new ground; GeSn FinFETs with a fin width below 10 nm that set a new benchmark for transconductance; and tuneable InGaAs nanomenbrane photoFETs on flexible substrates, which are promising for lightweight, wide-angle imaging applications.

Superior sub-threshold swing

Makers of these record-breaking tunnel FETs, Alireza Alian and co-workers from imec, Belgium, claim that their best devices, which sport a vertical nanowire architecture, produce a record transconductance of just 47 mV/decade. This low value is important, because it allows the device to operate at a lower power supply voltage while still delivering a high current. For imec's leading FETs, the drive current is 700 μA/μm at 0.35 V, for a fixed off-current of 1 nA/μm. That voltage is far lower than that used in today's ICs, which operate at around 0.9 V, highlighting the promise of III-V tunnel FETs for all mobile applications, where they could lengthen battery life.

imec's best results were obtained with nanowires with a 30 nm diameter. For insertion in a future node they would need to be "somewhere around ten nanometres", says Alian.

Another group in Europe, based at Lund University, have also produced encouraging results with vertical nanowire devices. "They did it using grown wires," says Alian. "We got quite similar results by etching the wires."

In Alian's view, the top-down approach that he and his co-workers adopt is better suited to high-volume manufacture. "It is believed to be more controllable "“ and less variability is expected than when you grow the wires."

Fabrication of imec's tunnel FETs begins with the growth of III-V layers on an InP substrate. The researchers employ this growth process, rather than MOCVD, because they believe it produces better interfaces. "CVD is usually at a higher temperature than MBE, so intermixing at interfaces is more severe," argues Alain.

The team produced a range of tunnel FETs, formed from nanowires with diameters of either 30 nm, 50 nm, 70 nm or 90 nm. Electron beam lithography defines their diameter, prior to etching into the heterostructure at 100 °C with a methane-based plasma to create these structures. Atomic layer deposition adds a gate oxide, comprising 1 nm-thick Al2O3 and 2 nm-thick HfO2. Fabrication finishes with the addition of a top spacer, top and back contacts, and in some cases an anneal in forming gas at 350 °C (see Figure 1 for a device architecture).

Figure 1. Formation of imec's tunnel FET begins with the growth of a heterostructure by MBE, and the use of lithography to define the diameter of the nanowires (a). Dry etching forms the nanowires (b), before a gate stack is added by atomic layer deposition (c), and a top spacer and top and back contacts are introduced (d).

Measurements on various devices, which have been studied with several microscopy techniques (see Figure 2), reveal significant variations in the drive current and the threshold voltage for transistors with the same nanowire diameter. These variations, which could be addressed by optimising the process, are attributed to unintended differences in doping and nanowire diameter.

Alian and co-workers observed a negative differential resistance in the output characteristics of their transistors, confirming that device behaviour is dominated by tunnelling. Performance improves with annealing in the forming gas, thanks to a reduction in the density of interface traps in the InGaAs layer.

A sub-threshold voltage below 60 mV/decade is only observed in devices with a nanowire diameter of 30 nm and 50 nm. This suggests that narrower wires improve sub-threshold voltage, a conjecture backed by simulations of the band-to-band tunnelling current "“ they indicate that shrinking the nanowire diameter to 20 nm could decrease the subthreshold swing to 20-30 mV/decade.

Any shrinking of the diameter of the nanowires must go hand-in-hand with increases in the source doping and a reduction in gate-source overlap. "Achievinghigher doping is not difficult," says Alian, who believes that it is easy to realise levels of 5 x 1019 cm-3. "For the overlap, it is possible, but variability is expected to become an issue." However, this can be addressed by engineering.

Alian and co-workers are hoping to now investigate the effects of higher doping. After this, the team may go on to study devices with narrower diameters.

Very fine fins

A claim for record-breaking miniaturisation came from a partnership between the National University of Singapore, Nanyang Technological University and Applied Materials. This collaboration believes that it has broken new ground by making GeSn pFETs with a fin width below 10 nm. The width at the top of the fin, produced on a 200 nm GeSn-on-insulator substrate, is just 5 nm.

Figure 2. Scanning transmission electron microscopy of the tunnel FET produced by the team at imec (a) can reveal the high quality of the InGaAs and GaAsSb layers (b).

This is not the ultimate limit, though "“ team spokesman Xiao Gong from National University of Singapore believes that optimizing the sidewall angle of the GeSn fin could lead to even smaller fin widths of about 3-5 nm. "The question is, at such small fin width, how high a mobility or source injection velocity can we achieve."

Gong says that the team's devices, which could make an impact at the sub 3 nm node, are produced with a process that is repeatable and straightforward.

Figure 3. (a) Darkfield transmission electron microscopy images of the GeSn p-finFETs produced by the team from the National University of Singapore, Nanyang Technological University and Applied Materials. (b) A highresolution transmission electron microscopy of a GeSn fin surrounded by the high-κ dielectric and the metal gate.

"The GeSn fins were first formed using an ICP dry etch to achieve a smallest fin width of about 15 nanometres. A digital etch process was then employed to trim it down to sub-10 nanometres."

The only step in the fabrication process that is not suitable for high-volume manufacturing is the patterning of the wafer by electron-beam lithography. But Gong says that this weakness can be overcome by turning to optical lithography.

Fabrication of the devices begins with CVD of a 10 nm-thick film of Ge0.95Sn0.05 on a silicon substrate. Using Ge0.95Sn0.05, rather than pure germanium, leads to a 55 percent hike in high-field hole mobility, according to experiment.

The next steps in device fabrication are: the definition of the channel; source and drain implantation, using boron; activation of the dopants, by heating the wafer to 400 °C for 60 s; forming the fins with a chlorinebased ICP etch, and then trimming with a digital etch; adding a gate stack, using process temperatures below 250 °C; etching the gate; and adding source and drain contacts (see Figure 3 for images of the devices).

A range of FinFETs have been produced with channel lengths from 50 nm to 200 nm, fin widths from 9 nm to 20 nm, and fin heights of 30 nm.

Measurements reveal that the smaller the fin width, the greater the suppression of short-channel effects. This helps to lower the sub-threshold swing, which fell from a minimum of 90 mV/decade for FETs with a 30 nmwide fin to a minimum of 63 mV/decade for a variant with a 9 nm-wide fin.

Other important characteristics of the transistors are a transconductance that can be as high as a record-breaking 900 μs/μm, an on-current that can hit 420 μA/μm at 1 V above threshold, a high hole mobility (see Figure 4) and an on-off ratio of 104. When judged in terms of the ratio of transconductance to saturated sub-threshold swing, the team's best device hits 10.5, a value that is claimed to be a record.

The 200 mm GeSn-on-insulator substrate used by the team from the National University of Singapore, Nanayang Technological University and Applied Materials to produce sub-10 nm pFETs with a record-breaking ratio of transconductance to saturated sub-threshold swing.

This figure-of-merit is important, according to the team, because it captures several key metrics. "Saturated sub-threshold swing gives you the information of the gate stack quality and on-off ratio for the current at a high drain-source voltage," says Gong, while the transconductance indicates the drive current that may be realised in the on-state. "For a transistor, we would like the ratio of transconductance to saturated sub-threshold swing as high as possible."

Figure 4. The effective mobility as a function of inversion carrier density, for GeSn pFETs produced by a partnership between researchers at the National University of Singapore, Nanyang Technological University and Applied Materials.

One of the next goals for the team is to replicate the good performance of the sub-10 nm GeSn p-finFETs with GeSn n-finFETs. "Gate stack and source/drain engineering for nFETs will be done to reduce the interface trap density and reduce the source/drain series resistance," explains Gong, who reveals that the team may also investigate the use of GeSn as the channel in TFETs.

Flexible photo-transistors

Two major changes in the coming decades will be the introduction of smart vehicles and autonomous drones. Both will benefit from lightweight imagers operating in the near and short-wave infrared "“ and if these devices could cover large surfaces, alongside detectors, they could also aid the development of ultra-light machines with wide-field imaging capability.

Figure 5. Researchers at imec and the National University of Singapore create a flexible, high performance device by using epitaxial lift-off to mount, on a polymer, an InGaAs-on-InP MOSHEMT with an exposed InGaAs channel.

A promising option for such detectors is being pioneered by a team from imec and the National University of Singapore. Their approach, detailed at the latest VLSI meeting, involves the use of epitaxial lift-off to expose the InGaAs channel of an InGaAs-on-InP MOSHEMT and create a flexible device that is more sensitive than existing silicon and III-V photodetectors in the near and short infrared (see Figure 5).

Spokesman for the team, Yida Li from the National University of Singapore, says that the motivation behind this is the aim of building a device that is flexible and lightweight. "This may allow us to enable imaging arrays on large-area surfaces to replace bulky hyperspectral imagers."

Li and co-workers decided to detect the light with high-quality layers of InGaAs, which they believe offer some advantages over more popular, but less mature, two-dimensional materials, such as graphene and MoS2. "We have exploited one key advantage of thinfilm devices by lifting off and inverting the device, to increase its photosensitive area, while allowing it to be flexible," argues Li.

Figure 6. The photoFET is fabricated with a series of steps that include spin-coating, epitaxial lift-off and exposure of an InGaAs channel.

Fabrication of the photoFETs begins with the growth of an InGaAs MOSHEMT on an InP substrate. Following meas isolation and the routing of electrode contacts to the field area, this epiwafer is bonded to an epoxy-based negative photoresist, SU-8, before the InP substrate is removed and the InGaAs channel exposed (see Figure 6 for details)

"The SU-8 is used to protect the photo devices from the chemical etch process, as well as to serve as a flexible backing for the ELO devices," explains Li.

He believes that these detectors could be produced with high-volume processes. "In this work, we explored the transfer of complete devices with metallization. This may allow for entire arrays of connected devices to be transferred rather than individual devices, leading to increased density and throughput." Alternatively, production could draw on high-precision heterogeneous pick-and-place, which Li says is a base technology in advanced wafer-level packaging.

The photoFET, on a polymer substrate, shows no signs of degradation when flexed with a radius of 10 cm.

Device measurements reveal that for a gate bias range of 6 V, photocurrent can be tuned by over five orders of magnitude. The on-state photoresponsivity is 380 A/W at 660 nm, and 15 A/W at 1877 nm, values that are claimed to be more than double those for existing silicon and III-V photodetectors. No degradation in performance is observed when the device is flexed with a radius down to 10 cm.

To improve performance in the short-wave infrared, the team can adjust the composition of InGaAs. "There is nothing that stops us from lowering the bandgap with higher indium content or moving to a lower-bandgap III-V for longer wavelength sensitivity," says Li, who points out that such a move would need to strike a balance between dark current leakage and sensitivity.

Figure 7. The responsivity of the InGaAs photoFET is far higher than that of many rival technologies.

The next goals for the team are to improve device performance through optimisation of the process, and to investigate opportunities to scale up to larger arrays.

This effort, and those that have led to record values for both the sub-threshold swing of vertical nanowire tunnel FETs and for the transconductance of GeSn pFETs with sub 10 nm fins, highlight the innovation within the compound semiconductor industry. Further breakthroughs in these areas will be reported at next year's VLSI "“ and prior to that, at the next IEDM, to be held on 1-5 December in San Francisco.