On the high-frequency frontier with InAlN-based HEMTs

Combining InAlN/GaN HEMTs with GaNOI technology ensures the monolithic integration of high-frequency GaN devices with CMOS technology.

BY HANCHAO LI AND GEOK ING NG FROM NANYANG TECHNOLOGICAL UNIVERSITY, YUE WANG, SHUYU BAO, KENNETH E. LEE FROM SINGAPORE-MIT ALLIANCE FOR RESEARCH AND TECHNOLOGY, HANLIN XIE FROM INSTITUTE OF MICROELECTRONICS, AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, AND EUGENE FITZGERALD FROM MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Within the family of compound semiconductors, GaN is held in particularly high regard. This material is renowned for its many strengths, including its wide bandgap, its high critical electric field, and the high density present in its polarisation-induced two-dimensional electron gas (2DEG).

One device that draws on these merits is the GaN-based HEMT, which outperforms its silicon-based counterpart. Thanks to the robust power-handling ability of GaN, this class of HEMT is well suited to serving in millimetre-wave applications in wireless communication technologies.

While GaN outperforms silicon, it cannot match its maturity. This makes the integration of GaN and silicon CMOS technology attractive, creating a marriage that offers a cost-effective scalable solution by leveraging existing silicon infrastructure while capitalising on GaN’s superior efficiency and thermal stability. However, it is easier said than done. Integration poses notable challenges, particularly in preserving the breakdown voltage and ensuring optimal RF performance.

Figure 1. GaN-on-insulator (GaNOI)-on-silicon wafers are produced by adding an insulating layer between the GaN epilayers and the silicon substrate.

Taking on these challenges, our collaborative team from the Singapore-MIT Alliance for Research and Technology, Nanyang Technological University, and Massachusetts Institute of Technology, is pioneering the use of wafer-bonding technology to enable a GaN-on-insulator (GaNOI) architecture on a silicon substrate.

It’s an effort that’s been underway for several years, with our initial success presented at the VLSI Symposium 2019. At that meeting we reported validation of the enhanced breakdown voltage of the GaNOI structure and its compatibility with silicon CMOS technology.

Our innovative method, described in prior reports, enables the processing of large silicon wafers in standard silicon foundries. Using this approach, we have enhanced device reliability by eliminating the initial transition layer, characterised by a multitude of dislocations and subpar thermal conductivity.

Figure 2. Cross-sectional InAlN/GaN heterostructure schematic showing the location of the 2DEG and energy band diagram of a GaN heterostructure.

Another refinement has been substituting the original silicon (111) substrate, which is prone to fragility after high-temperature GaN growth, with a more robust silicon (100) substrate. This switch significantly diminishes the likelihood of wafer breakage during production, leading to increased yield.

More recently, we have started to explore the potential of GaNOI technology in high-frequency applications. By constructing GaN HEMTs on an insulating substrate, GaNOI technology is expected to trim parasitic capacitance and ultimately improve frequency performance.

Typically, GaN-based HEMTs employ either AlGaN, InAlN or AlN as the barrier material. The selection from these three has a great influence on overall device performance and reliability, especially under harsh conditions, such as high temperatures.

The 2DEG that forms at the interface between the barrier layer and GaN lies at the heart of the HEMT, acting as a quantum well filled with high-mobility electrons. Levers for optimising the properties of the 2DEG, such as its density and mobility, include varying the thickness and the material composition of the barrier layer.

Figure 3. Reported f_T/f_max values for various GaN-on-silicon HEMT technologies.

Traditionally, AlGaN has been the go-to material for the barrier layer. However, it is not without weakness. A significant downside is the stress induced by the piezoelectric effect, leading to possible lattice defects.

This is where InAlN comes in to play, offering a compelling alternative that’s lattice-matched to GaN, thus minimising strain effects (see Figure 2). Switching to InAlN is the move behind record current-gain cut-off frequencies, which indicate the potential of InAlN/GaN HEMTs in high-frequency applications.

To date, the highest cut-off frequency for AlGaN/GaN HEMTs on silicon substrates is 152 GHz, realised with devices with a recessed gate that have a 75 nm gate length. With this particular device, an AlGaN barrier layer thickness of 25 nm results in 2DEG density of 1 × 10¹³ cm^-2. By replacing this with an InAlN barrier, the thickness of this layer can be trimmed to around 8 nm, while realising an even higher 2DEG density, in the range 1.2 - 1.7 × 10¹³ cm^-2. This improvement is due to a higher spontaneous polarisation for InAlN/GaN, compared with AlGaN/GaN. The thinning of the barrier layer while maintaining a high sheet carrier density is desirable, enabling increased gate modulation control by reducing the gate-to-channel distance, and ensuring an increase in transconductance. With an InAlN/GaN HEMT on silicon, we have recorded values for the cut-off (f_T) and maximum oscillation (f_max) frequency of 300 GHz and 400 GHz, for a 30 nm gate length (see Figure 3).