Gallium oxide MOSFETs: Why interfaces matter

Developers of gallium oxide power devices should draw on lessons learnt from the pioneers of compound semiconductor MOSFETs.

BY IAIN THAYNE FROM THE UNIVERSITY OF GLASGOW

Thanks to its ultra-wide bandgap (UWBG), alongside availability of native substrates, β‑Ga₂O₃ is steadily transitioning from an intriguing laboratory material to a serious option for next‑generation power electronics. For researchers and technologists pursuing that goal and working across materials, devices, and integration, the central question is no longer whether gallium oxide channel transistors are scientifically interesting, but how – and how quickly – they can be translated into a robust, scalable device platform that aligns with realistic application and qualification requirements.

It is evident that today’s gallium oxide MOSFETs remain at an early stage of technical maturity. Threshold voltages tend to lie on the wrong side of zero, subthreshold swings are well above the thermal limit, and there’s a paucity of published reliability data. However, none of these observations are fundamental showstoppers. Rather, they reflect an emerging MOS technology, where progress in channel material development outpaces refinements in interfaces and gate stacks.

Many of the challenges now confronting gallium oxide are neither unprecedented nor unsolved. As is often the case, delving into the journals of yesteryear can speed development.

For today’s developers of Ga₂O₃ MOSFETs, valuable insight can be gained from revisiting earlier work on GaAs siblings, where sustained effort was devoted to interface control, gate‑stack chemistry, and charge management. Papers by pioneers of GaAs MOSFETs provide a convincing demonstration that high‑performance MOS operation is achievable, even though the industrial demand required for large‑scale adoption did not ultimately emerge at the time.

A recurring challenge: the MOS interface
Whenever a semiconductor material is proposed as a MOSFET channel, the focus quickly shifts from bulk properties to the gate interface. This makes much sense. After all, the interface is crucial, as it is where there’s a transition from a crystalline semiconductor to an amorphous dielectric, a change that almost inevitably has the potential to introduce electronic defect states that degrade electrostatics, increase variability, and complicate reliability. One need look no further than the historical development of the silicon MOSFET to see that the ability to control this interface will often determine whether a material system advances from demonstration to deployment.

Gallium oxide is at this inflection point. Many reported β‑Ga₂O₃ MOSFETs exhibit large subthreshold swings and threshold voltage instability, behaviour consistent with significant charge trapping, occuring at or near the gate dielectric interface. While there have been impressive advances in crystal growth, substrate availability, and doping control, the same cannot be said for interface engineering. Here, progress is slower, mirroring events in earlier compound semiconductor development cycles.

Figure 1. Standard gate dielectric screening methods probe defects/traps with energies across virtually all of the bandgap in silicon-based devices (left). In contrast, for Ga₂O₃-based devices (right), trap/defect states with a wide range of energies around mid-gap go undetected. As a consequence, dielectric trap state densities will be underestimated. This is why transistor sub-threshold swing is a better metric for dielectric screening in Ga₂O₃ MOSFETs.

Lessons from GaAs MOSFET research
During the late 1990s and early 2000s, GaAs MOSFETs were intensively investigated for RF and logic applications. The motivation behind this is that GaAs offers outstanding carrier transport. However, this binary also suffers from well‑known surface chemistry challenges, historically limiting MOS device operation. Through the focused research of that time, it was shown that these challenges are not fundamental.

One of the milestones of that era was the development of chemically compatible amorphous gate stacks. Introducing ultrathin gallium‑oxide‑based interlayers and carefully selecting ternary gadolinium-based high‑k dielectrics with related chemistry enabled the fabrication of GaAs MOSFETs with a low interface state density, near‑ideal subthreshold swing, and positive threshold voltage. Crucially, these improvements were maintained through realistic fabrication sequences, demonstrating that these interface solutions were not merely laboratory artifacts.

Ultimately, GaAs MOSFETs with these highly engineered gate stacks did not enter large‑scale production. But that’s not because they failed to meet performance targets – it’s because alternative device technologies were a better match to system‑level needs, and the cost structures of the time. Nevertheless, the technical lessons learned – particularly regarding interface control – remain directly relevant to today’s UWBG devices.

For those currently working on gallium oxide devices, a noteworthy finding from previous GaAs MOSFET development is the potential of appropriately selected ternary gadolinium-based high-k materials, deposited optimally on Ga₂O₃. More generally, though, there’s an underlying philosophy to take onboard – identifying amorphous dielectrics, engineered specifically for chemical compatibility with Ga₂O₃, deserves attention. Unfortunately, much current work involves incremental surface treatments, followed by deposition of conventional dielectrics. While this strategy delivers measurable improvement, it may fail to provide the degree of interface control needed for stable enhancement‑mode operation, low variability, and acceptable lifetime under bias.

Switching to more fundamentally engineered gate stacks, combined with appropriate interlayers, promises to suppress interface trap formation systematically, rather than reducing their impact indirectly. For UWBG semiconductors, where deep traps exhibit slow dynamics and long recovery times, this distinction is particularly important from a device‑physics and qualification perspective.

Subthreshold swing: A practical indicator
In gallium oxide MOSFETs, subthreshold swing is a particularly useful metric for assessing interface quality. In both wide and ultra-wide bandgap materials, many electrically active states lie deep in the bandgap, making them difficult to probe with the conventional capacitance‑based techniques, which were developed to screen oxides for silicon MOS devices as illustrated in Figure 1. Subthreshold swing, by contrast, reflects the cumulative impact of these states on channel formation and electrostatic control.

Based on this state of affairs, as gallium oxide devices mature, convergence toward lower and more reproducible subthreshold swing values will be a key indicator that interface‑related challenges are truly being addressed. From an application standpoint, improvements in this metric are closely linked to threshold voltage stability, device‑to‑device uniformity, and ultimately manufacturability.

Architecture considerations
Beyond gate materials, device architectures play an important role. During the development of GaAs MOSFETs, heterostructure channels were used to spatially separate carriers from the oxide interface. This led to reduced carrier interaction with interface states. Similar ‘thin spacer layer’ concepts are now being explored in gallium oxide, through the use of aluminium‑ and indium‑containing oxide alloys.

While one should not underestimate the materials challenges associated with such heterostructures, if successful implementation is realised, this could complement advances in gate stack design. In turn, this could ease interface requirements and expand the available design space for gallium oxide devices.

Towards application readiness
The path from promising research devices to application‑ready power transistors is defined by more than headline performance metrics. As technologies move closer to deployment, it becomes increasing important to consider the likes of variability, bias stability, endurance under stress, and reproducibility across a wafer. Tightly coupled to each of these considerations is interface quality.

In the near term, if there is meaningful market penetration for gallium oxide MOSFETs, this will probably be associated with grid-level power infrastructure, solid-state protection, pulsed-power systems, and specialised industrial or aerospace platforms. For these applications, scaling volume is not a standout priority. What also matters is realising sufficient confidence in gatestack reliability, having thermal management strategies, and achieving long-term stability under realistic operating conditions. Success in these early application spaces would represent an important step toward application readiness, establishing gallium oxide as a credible UWBG option for demanding voltage regimes, and laying the groundwork for broader adoption as system requirements evolve.

Development of the GaAs MOSFET shows that it’s possible to produce high‑quality MOS interfaces on compound semiconductors by addressing chemistry, structure, and processing holistically.

Optimisation of the gallium oxide MOSFET may benefit from leaning into these approaches, and leveraging knowledge surrounding gadolinium-based high-κ dielectrics deposited on Ga₂O₃, as well as the judicious use of hetero-interfaces.