HfO₂ for better GaN transistors

Introducing a HfO₂ gate dielectric improves the vertical GaN transistor, boosting its drain current density and its breakdown voltage.

BY ENRICO BRUSATERRA, ELDAD BAHAT TREIDEL, PALLABI PAUL, MARTIN DAMIAN CUALLO, FRANK BRUNNER, INA OSTERMAY AND OLIVER HILT FROM THE FERDINAND-BRAUN-INSTITUT, BERLIN

The lateral GaN HEMT is without doubt a great success, generating significant sales that will continue to climb to billions of dollars per annum by the end of this decade. But despite the ramping revenues, it’s not the best geometry for this higher class of power device. The vertical architecture has the upper hand on a number of fronts, promising a higher breakdown voltage, a higher on-state current, a reduced resistance and a lower thermal impedance for a given chip size.

In addition to all these advantages, the vertical device has another valuable asset – it provides a normally-off behaviour, with a positive threshold voltage required to turn the transistor on. This characteristic is a mandatory requirement for safe, high-power operation.

Developers of vertical transistors tend to use gates that are either based on metal-oxide-semiconductors or junctions. Of these two, it’s only a variant of the former, the inversion-type MOSFET, that provides a sufficiently high positive threshold voltage required for fail-safe normally-off operation, alongside a low gate leakage current necessary for stable operation in a noisy power-electronic environment.

Within the family of vertical GaN MOSFETs, those with a trench-gate architecture are the most common. A key merit of this design is that it allows the p-type GaN channel-layer to be formed by epitaxial growth, thereby avoiding the need for ion implantation of magnesium, followed by successive activation during the fabrication process. Such activation is not ideal, demanding lengthy annealing above 1300 °C, a temperature so high that it already decomposes the GaN crystal. What’s more, as the processing of the trench MOSFET does not require particularly high-resolution lithography, these transistors can be produced with a higher yield and a lower cost than other architectures, such as FinFETs.

One of the requirements for the gate module is that it has an electrical connection to all three epitaxial layers: drift, channel and source. To fulfil this requirement, a trench is etched into the epitaxial stack prior to deposition of the gate dielectric and the gate metal.

When operating the trench MOSFET, electrons in the p-GaN layer, induced by a positive gate bias, form the transistor inversion-channel. During device processing, trench-etching damage may occur, slowing electron transport. Causes include interface roughness and the formation of defect states at the interface of the GaN and the gate dielectric at the trench side-walls. Due to this, channel electron mobility can be quite low.

An undesirable consequence of this state of affairs is that it’s hard for trench MOSFETs to achieve channel mobilities and switching speeds as high as those in planar gate devices.

For engineers employing modern GaN-based semiconductor technology, there are two primary options for the gate dielectric of the trench MOSFET. For production purposes, SiO₂ is preferred, due to the higher throughput of low-pressure CVD machines; and for research and development, Al₂O₃ is the standard, as high-quality thin layers can be deposited with atomic layer deposition, and this oxide is a well-established high-κ dielectric in the semiconductor industry.

To improve the performance of the trench MOSFET, our team at Ferdinand-Braun-Institut, Berlin, is pioneering a new gate dielectric, consisting of a stack formed from HfO₂ and Al₂O₃. This pairing is designed to combine a high relative dielectric constant with a low interface trap density and the realisation of a small threshold voltage shift, as typically observed for pure Al₂O₃ layers. A high dielectric constant is very desirable, as it increases inversion charges in the p-type channel, as well as helping manage the electric field inside the gate trenches.

Figure 1. Publication trend of the last 20 years on HfO₂ in general, and in combination with GaN

Selecting HfO₂ is not a surprising choice, given that this oxide has gained a growing popularity for GaN-based transistors (see Figure 1). Merits of HfO₂ include a very high relative dielectric constant of around 20, while still maintaining a high enough bandgap – it is around 5.4 eV – and, more importantly, a good band offset to both the GaN conduction (1.1 eV) and the valence (1.6 eV) band. HfO₂ is also a tried and tested material in the semiconductor industry, having been developed for silicon-based applications in DRAMs since 2007.

To ensure that we can work with this oxide in our standard trench MOSFET process line, we tested the material properties of HfO₂, and its stability to other process steps. This investigation determined that HfO₂ is stable up to 350 °C, shows signs of decomposition at 500 °C, and starts to crystallise at 550 °C.

Based on these findings, we know the extent of the temperature budget available for all the process steps for transistor fabrication after oxide deposition. Another factor influencing oxide stability is the surface quality of GaN. We discovered that ammonia plasma-treated surfaces are more stable overall. In addition, plasma cleaning helps reduce oxygen impurities at the GaN surface, leading to improved electrical performance for the dielectric.

We have compared our new dual material dielectric with our standard gate technology that’s based on just Al₂O₃. Our stacked oxide consists of 60 percent hafnium and 40 percent aluminium, a combination that provides a relative dielectric constant above 15 while maintaining a low interface trap density associated with the Al₂O₃ component of below 4 x 10¹² cm^-2, and a high breakdown field provided by HfO₂ of 6.6 MV cm^-1. Another encouraging finding is that our combined oxide is more than twice as stable to voltage-induce stress as either just Al₂O₃ or just HfO₂. This robustness is especially beneficial for transistors, as exposing the gate to voltage stress may induce a shift in threshold voltage and ultimately instability during operation.

Our newly developed dielectric stack has been implemented in our standard trench-MOSFET process line. We have produced devices on 2-inch ammonothermally-grown bulk GaN substrates provided by the Institute of High-Pressure Physics of the Polish Academy of Science (for more details, see the papers listed in ‘Further Reading’). The design of this trench MOSFET and details related to epitaxy are provided in Figure 2.

Figure 2. (left) An image of a multi-cell trench-MOSFET cross-section taken using focused ion beam (FIB). (Right) A device schematic diagram.

Electrical measurements on our trench MOSFETs with the novel stacked gate dielectric reveal that compared to that with a standard Al₂O₃ gate dielectric, forward current is up to three times higher, and there is a substantial reduction in the threshold-voltage shift induced by positive gate-bias stress. Another strength is the much higher channel mobility of 11.1 cm² V^-1 s^-1. Thanks to this, on-state resistance falls by a factor of three, despite no apparent difference in accumulation capacitance or threshold voltage.

We explain these phenomena by considering that, for the same gate capacitance, the two different dielectrics are exposed to very different electric fields, given the different oxide thicknesses of 25 nm and 50 nm needed to maintain the same input capacitance. A lower electric field inevitably reduces trapping effects in the oxide. The diminished electric field that reduces interface trapping accounts for the superiority of our trench MOSFET with a gate that features both HfO₂ and Al₂O₃.

Figure 3. Photo of a packaged trench MOSFET with 1800 mm gate periphery processed by the Ferdinand-Braun-Institut (FBH).

Incorporating HfO₂ into the gate stack increases the breakdown voltage of the gate modules. With HfO₂, a 50 nm-thick dielectric can handle up to 250 V, while the standard Al₂O₃-based dielectric only withstands 50 V over 25 nm. Our measurements have determined that the breakdown voltage of transistors that incorporate HfO₂ are 410 V. Testing our trench MOSFETs with the new gate dielectric under high-voltage switching conditions produces promising results (a photo one of these transistors, which have a large gate periphery of 1800 mm that’s designed to deliver high currents, is shown in Figure 3). When stressing these devices under a high voltage in their off-state for 10 ms, we monitored the drain current after turn-on for another 10 ms (results are shown in Figure 4). Operating at an off-state drain bias of 360 V, on-state resistance degraded by only 50 percent, increasing from 16.7 mΩ cm² to 25.6 mΩ cm². Note that the correlation between the dynamic on-state resistance and off-state drain voltage is not typical degradation due to hot electrons (this is common in lateral GaN HEMTs, where current flows close to the surface and is sensitive to the presence of localised charges and defects).

Figure 4. Dynamic switching characteristic of a trench MOSFET with HfO₂ gate dielectric. After 10 ms off-state stress with 20-360 V drain bias, the transistor is turned on by switching the gate bias from 0 V to 15 V. The on-state drain current is monitored for 10 ms at 10 V drain bias.

Following in-depth analysis, based on the degradation of the on-state resistance over time, we concluded that for low stress biases, the non-depleted part of the drift region interacts with the gate trench, showing a wide range of traps and defects. This situation differs for high stress biases. In this case, the portion of the drift region close to the trench is fully depleted, making interaction less likely. This suggests that the degradation of on-state resistance is related to the gate trench itself, and suggests that improving the dielectric interface to the GaN inside the trench can advance the switching performance of the trench MOSFET.

With interest in GaN power electronics increasing, and efforts at launching commercial vertical GaN transistors underway by both start-ups and established chipmakers, our efforts provide a timely development on how to improve the performance of these most promising of devices.

Further reading
E. Brusaterra et al., “Vertical GaN Trench MOSFETs With HfO₂ / Al₂O₃ Layered Gate Dielectric,” in IEEE Trans. Semicond. Manuf 38 750 (2025)

P. Paul et al. “Plasma enhanced atomic layer deposition of HfO₂ – A potential gate dielectric for GaN-based devices,” in J. Vac. Sci. Technol. A 43 042406 (2025)