IEDM: Turbo-charging the transistor
At a session at the International Electron Devices Meeting devoted to 6G and terahertz applications, engineers unveiled new strategies for increasing the operating frequency of the transistor
BY RICHARD STEVENSON, EDITOR, COMPOUND SEMICONDUCTOR
As the roll-out of 5G gathers pace, engineers in academia and industry are considering what might follow. Towards the end of this decade and beyond, wireless communications is tipped to move to higher frequencies – almost certainly beyond 100 GHz, and possibly encroaching the terahertz domain.
While the next step on the wireless roadmap, 6G, is yet to be defined, it is expected that initial research into this communication standard will focus on the D-band, which spans 110 GHz to 175 GHz. However, when 6G is actually deployed, it is likely to operate within the 300 GHz to 450 GHz frequency range. Circuits operating at such high speeds will need to combine high frequencies with a high power efficiency and multi-functionality, a set of conditions that is hard to satisfy with silicon CMOS. Offering more promise are heterogeneous technologies that marry the merits of silicon, such as maturity and high-volume manufacture, with the superior speeds of the III-Vs.
Efforts in this direction were discussed in session at the 2021 International Electron Devices Meeting (IEDM) entitled Microwave, Millimetre Wave and Analog – III-V technologies and their application to terahertz/6G. In that session, taking place in San Francisco in early December, Intel championed its record-breaking enhancement-mode GaN transistors produced on 300 mm silicon, and a team led by KAIST claimed to break new ground with InGaAs HEMTs on silicon. Other teams reported their successes with III-V transistors on native substrates, potentially providing a stepping-stone to triumphs on a silicon foundation. A partnership between engineers in South Korea and NTT detailed InGaAs-on-InP HEMTs with record-breaking frequencies, while researchers at ETH Zurich unveiled terahertz transistors based on GaAsSb and InP that are fabricated with a new process that provides optimisation of the base-emitter access distance.
Figure 1. (a) Intel’s E-mode GaN transistor has an fT of 300 GHz and an fMAX of 400 GHz. (b) A transmission electron microscopy image shows the gate length is just 29 nm.
At IEDM Intel made many record-breaking claims for its GaN-on-silicon transistors, including new benchmarks for the cut-frequency (fT) and maximum oscillation frequency (fMAX), two key figures-of-merits. Further firsts included: the highest transconductance, attributed to device scaling and the incorporation of a material with a high dielectric constant; a record-breaking drain-source voltage for this class of transistor; and the fabrication of the first truly E-mode GaN transistor that delivers a full on-current, realised with a record low-gate drive of just 1.8 V (typically, E-mode GaN HEMTs need a gate drive of at least 6 V). In addition, Intel’s GaN-on-silicon transistors were said to provide an outstanding RF performance.
According to Han Wui Then, spokesman for the Intel team from Hillsboro, Oregon, their successes have come from insights provided by Moore’s law and Dennard MOSFET scaling. To draw on this, they developed a process for producing E-mode transistors with gate lengths down to 30 nm. Their fabrication involves the use of a high-k dielectric technology, an atomic layer etch, and GaN buffer technology.
Intel’s spokesman is in no doubt that the best material system for such efforts is GaN, describing this as “the technology of choice for ultra-fast switching and for producing compact integrated power electronics and RF millimetre-wave”.
The team’s GaN transistors, formed on silicon (111) substrates, feature a recessed gate and low-resistance re-grown source and drain contacts (see Figure 1 for a device diagram). Circuits that incorporate these devices are formed with a four-level copper backend interconnect process that can produce thin-film resistors and metal-insulator-metal capacitors (see Figure 2).
Figure 2. (a) Intel’s high-speed ICs are formed using a four-layer copper back-end stack that includes metal-insulator-metal capacitors and thin-film resistors. (b) A scanning electron microscopy image, showing the fabricated copper backend interconnect over E-mode high- dielectric GaN transistors fabricated on 300 mm silicon.
“Our 300 millimetre process is highly uniform,” argued Then, who pointed out that the one-sigma variation in threshold voltage is just 38 mV. He added: “This enabled us to fabricate and integrate a large number of gates”. He gave an example of a power GaN die with a total width of 880 mm and an area of just 4 mm2. This chip is capable of a power density of 9 A mm-2.
Attributes of Intel’s GaN transistors include a very low leakage current, a high drive current, a low on-resistance, and a capability to withstand a drain-source voltage up to 65 V. A common figure-of-merit for power electronics – the product of on-resistance and the gate charge – suggests that Intel’s GaN transistors are 14 times better than discrete GaN and silicon LDMOS devices (see Figure 3). “This gain truly shows the power of scaling when applied to high-k gate dielectric gallium nitride transistors,” claimed Then. Intel’s GaN transistors combine an impressive performance with a high level of reliability. Operating at 90 °C with a drain-to-source voltage of 10.5 V, time to failure – defined as a degradation in the drain current by 10 percent – is 10 years.
Figure 3. Channel length scaling improves the power delivery switch, according to a figure-of-merit that is defined as the product of on-resistance and the gate charge. One of the benefits of scaling is that it allows the construction of faster, more compact power electronics.
Studies by Then and colleagues have shown that shrinking device dimensions leads to a hike in transconductance. Decreasing the gate length from just over 2 µm to 30 nm led to a rise in transconductance from just over 1200 µS/µm to 2100 µS /µm.
Transistors with a 30 nm gate length and a gate-to-drain distance of 160 nm have an fT of 300 GHz and an fMAX of 400 GHz. For this device, the RF switch figure of merit – the product of the on-resistance and off-capacitance – is 70 fs. This as an “excellent number,” said Then.
He and his co-workers have also carried out load-pull measurements, considering a range of frequencies and various gate lengths. Results included a device with a 90 nm gate length producing an output power of 23.4 dB at 28 GHz, alongside a power density of 2.7 W/mm and a power-added efficiency of 50 percent. Increasing the frequency led to a reduction in output power and efficiency, with a saturated output power falling to 0.4 W/mm at 90 GHz, and power-added efficiency down to 10.5 percent.
The team from Intel are expecting GaN finFET architectures and 3D layer transfer technologies to play a significant role in the scaling of GaN transistors and the integration of more functionalities. According to Then, this could include a marriage of GaN and CMOS, to enhance the capabilities and reach of GaN technology.
He and his co-workers have already started to explore this possibility, using 3D layer transfer technology to unite silicon PMOS and GaN NMOS devices (see Figure 4). The latter, having finFET widths of just 35 nm, are claimed to feature the narrowest GaN fins ever produced. Device fabrication involved the bonding, cleaving and transfer of a thin layer of single-crystalline silicon onto a GaN transistor wafer, prior to completing the fabrication steps required to form the top silicon devices over the bottom GaN transistors.