News Article

Fujitsu Proves Reliability Of GaN HEMTs

Fujitsu's GaN program has led to proven device reliability, a fabrication process using low-cost conducting 3 inch SiC substrates, and record output power from MIS-HEMTs, says Toshihide Kikkawa.

Wireless mobile networks will continue to evolve, and from 2010 we can expect to see the roll-out of 4G services offering transmission speeds of more than 100 Mbit/s. These next-generation networks will require faster, more powerful transmission amplifiers that will consume more energy and take up more space. This could lead to larger base stations operating with higher running costs if the incumbent and relatively inefficient silicon LDMOS is deployed, and so efforts are being directed at developing alternative technologies, such as GaN HEMTs, for future networks.

These GaN HEMTs are efficient, can produce high output powers from relatively small chips sizes, and have higher breakdown voltages and cut-off frequencies than transistors based on other semiconductor materials. At Fujitsu we have already demonstrated highly efficient push-pull amplifiers based on this material delivering 250 W wideband code division multiple access (W-CDMA) signals. However, if these GaN transistors are to fulfill their promise and provide a viable alternative to silicon LDMOS, then improvements have to be made in terms of reliability, distortion, cost and gate leakage at high output powers.

At Fujitsu Laboratories in Kanagawa, Japan, we addressed all these issues by investigating the performance and refining the design of our GaN HEMTs. Our standard structure was used to study device reliability (see figure 1a), while modifications to the substrates and top structures provided reductions in cost and improvements in output power (see figure 1, b and c).Addressing failure mechanisms

Our reliability tests were carried out with the GaN HEMT mounted on a conventional metal/ceramic package. We addressed the mechanisms limiting reliability - transconductance dispersion and large-signal drain-current degradation, which is commonly known as current collapse - with a fabrication process that controls the polarization-induced surface charges with a moderately-doped n-type cap layer. This approach differs from that of many researchers, who use an AlGaN cap, or dope the GaN cap either more heavily or not at all. Our moderately-doped GaN cap is not fully depleted, and can suppress the strength of the electric field under the gate and screen the trapping effect.

We found that device degradation, which is the biggest obstacle to GaN HEMT commercialization, can occur on three different time scales: either just a few seconds, over one to two hours, or after several hours. The most rapid degradation produces an exponential increase in the gate leakage current and can be eliminated by improving the interface stability between the gate electrode and the GaN surface.

Sudden device failure can also occur after one to two hours of a high-temperature direct-current stress test and appears as a drain current spike (see figure 2). The likelihood of failure depends on the quality of the epitaxial layers and the processing steps. The transistor can still operate after it has degraded, and room-temperature leakage current measurements at low gate-source voltages cannot identify the damaged devices (see figure 3). However, if the test is repeated at 150 °C the defective device is exposed by a leakage current increase of two to three orders of magnitude.

We also witnessed a gradual degradation in the HEMT output power of less than 0.5 dB during a room-temperature P3dB-RF stress test (this compression test compares RF input and output signals, and determines the point at which gain falls by 3 dB from the linear gain that occurs at low input powers). This degradation depends on the process conditions of the surface layer and the quality of the buffer layer. We addressed these concerns by optimizing the transistor s pulsed I-V characteristics with fabrication process improvements, and produced devices with suppressed efficiency degradation (see figure 4). By preventing any device degradation on this, and the two far shorter time scales, we proved the reliability of the GaN HEMTs .

Cutting manufacturing costs

GaN HEMT prices will strongly depend on yield and consequently substrate quality. Today, many SiC substrates have pits that can reduce device efficiency - due to an increase in the source-drain current - if electrodes are deposited on top of these defects (see figure 5). This is not a significant issue for relatively low-power transistors that have gate electrodes of typically 1 mm, since the yield for these devices is only weakly dependent on pit density. However, hexagonal pit densities of less than 1 cm-2 are needed for the large-periphery gate die used for transistors delivering higher outputs, such as 100 W.

GaN HEMTs also need to have a low memory effect - a small value for the hysteresis between the input and output powers. This effect can be examined by looking at a third-order intermodulated signal that is produced from two signals and results from the non-linearity of the amplifier. This third-order signal is relatively weak over a wide frequency range, which is due to SiC s good thermal conductivity and high load impedance.

We also built GaN HEMTs on n-doped SiC, which could cut production costs by between two-thirds and one-half. These lower cost substrates offer a good mix of price and performance, because although they are not as cheap as silicon or sapphire, they produce the same thermal memory effect as semi-insulating SiC.

These substrates do have the problems that are associated with any conductive substrate, such as parasitic capacitance and isolation leakage, but we addressed these issues by inserting a 10 µm thick HVPE-grown AlN buffer between the transistor and a 3 inch SiC substrate (see figure 1b). The quality of the oxidized AlN layer strongly influences the GaN layers roughness and device performance (see table 1). The root-mean-square (RMS) value for surface roughness increased with scan area, and we found it was easier to discriminate between the different surfaces with these wider scans.Scaling it up

Two years ago, we reported that we could produce 100 W GaN HEMTs on 2 inch conductive SiC substrates, and now we are developing the transistors on 3 inch material because this will deliver lower manufacturing costs. However, large substrates bring their own problems, such as bowing, and MOVPE growth of the GaN HEMT structure produced an epiwafer bow of 8.7 µm. This level of deformation did not prevent the deposition of high-quality 0.8 µm long gates, and we were able to make 1 mm-gate-periphery GaN HEMT chips from the entire wafer. The transistors were operated at 60 V and delivered a continuous-wave output power density of 7.0 W/mm, and a power-added efficiency (PAE) of 70% at the 3G base-station transmission frequency of 2.14 GHz. Standard deviations for the power density, linear gain and PAE at 50 V across a whole wafer were 0.42 W/mm, 0.2 dB and 3%, respectively.

Next-generation networks will need to operate at higher efficiencies in order to reduce power consumption. This means that the GaN HEMTs will have to operate much closer to their saturation point, but this leads to very high gate-leakage currents that degrade the device s reliability and amplification characteristics. To address this issue we developed GaN metal-insulator-semiconductor (MIS) HEMTs (see figure 1c) that deliver 110 W output with no forward gate leakage (see figure 6). These devices avoid having a semiconductor surface in contact with an AlGaN insulating layer that can easily oxidize and degrade performance, and are the first insulated gate transistors that produce greater than 100 W. Initial reliability tests show that they have a stable leakage current over several hours.

Our GaN development program has addressed reliability issues in GaN HEMTs, demonstrated that these devices can successfully operate when grown on lower-cost conducting substrates, and led to the first GaN MIS-HEMTs capable of output powers greater than 100 W. We believe this progress shows that there is a very promising future for GaN transistors in tomorrow s wireless infrastructure market.

CS International to return to Brussels – bigger and better than ever!

The leading global compound semiconductor conference and exhibition will once again bring together key players from across the value chain for two-days of strategic technical sessions, dynamic talks and unrivalled networking opportunities.

Join us face-to-face between 28th – 29th June 2022

  • View the agenda.
  • 3 for the price of 1. Register your place and gain complementary access to TWO FURTHER industry leading conferences: PIC International and SSI International.
  • Email  or call +44 (0)24 7671 8970 for more details.

*90% of exhibition space has gone - book your booth before it’s too late!


Search the news archive

To close this popup you can press escape or click the close icon.
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.

Please subscribe me to:


You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
Live Event